Commit Graph

8 Commits

Author SHA1 Message Date
Travis Geiselbrecht
c55ab00668 [platform][sifive] add a GPIO driver and switch the target setup to it 2021-01-20 01:11:29 -08:00
Travis Geiselbrecht
90dc9e50ef [platform][sifive-e] get the hifive1 hardware working again
Had rotted a bit. Had to reimplement a few tweaks.
Also generally #if out a lot of the SMP code when unused on riscv.
2020-01-18 18:39:07 -08:00
Elliot Berman
d239adf839 [arch][riscv] Add basic support for SiFive HiFive Unleashed
Most of changes were moving around where macros were defined, plus the
following:
- Remove requirement for floating point on RV64 to support booting
  monitor core on U54 SoC.
- Add support for Debug LEDs on HiFive Unleashed Board
2020-01-16 23:06:28 -08:00
Travis Geiselbrecht
fdc08a8446 [arch][riscv] port to riscv64
Very little needed to port except to conditionalize some assembly in the
context switch and exception code. Mostly needed to move build system
stuff around and add a new project.
2019-11-02 17:21:13 -07:00
Travis Geiselbrecht
ae5200595c [platform][riscv-virt] added support for QEMU's riscv 'virt' machine
The virt machine is a generic target, much like the arm virt machine.
Intended to be simple to use and a good target to run large systems like
linux on. At the moment simply support booting and simple uart and timer
support.
2019-11-02 14:19:36 -07:00
Travis Geiselbrecht
63be190d8b [target][sifive-e] Get LK working on a Sifive Hifive1 board
-added support for bringing up the clocks and setting up the gpio bits
before starting the uart.
-add a proper target init routine
-add scripts to flash board via openocd
-fixed bug in riscv interrupt save state where it wasn't saving mstatus
on irq entry.
-comment out cycle enabling, not implemented on this core
2019-02-18 22:13:22 -08:00
Travis Geiselbrecht
a0a6b10e0b [arch][riscv32] rename the qemu target sifive-e
The initial port is really a Sifive E platform. Call it what it is and
make space for bringing up the Sifive U and virt qemu target.
2019-02-17 20:29:50 -08:00
Travis Geiselbrecht
8cf28bbdcf [arch][riscv] Initial port to a riscv32 sifive target
Currently targets qemu's sifive_e machine, which is a split flash/ram
machine, much like the Sifive HiFive1. Untested as of yet on a real
HiFive1.

Basic support including interrupts and architectural timers in place.
2018-12-16 16:44:23 -08:00