The issue was found on AMD machine when run lk with qemu kvm, it
can't boot if kvm hardware is enable in qemu.
According to Intel system programming guild Chapter 4 "Paging",
if the page table entry is non-leaf entry, then the G bit will be
ignored.
However, According to AMD programmer mannul Volume 2, Chapter 5.3
"Long-Mode Page Translation", the non-leaf page table entry G bit
must be zero.
The patch sets inner page table entry G bit to zero so that it
works on both Intel and AMD CPU
Add build system support for at least being aware of the FPU on
the architecture, not building code to use it.
At the moment, only sets up the FPU into Initial state prior to
entering user space and then ignores it.
For user space support, the sscratch register cannot hold the pointer to
the current cpu, as much as it is convenient.
Change the logic to use tp register (x4) to point to percpu, and
dereference the local thread from it directly.
Create a user space address space, map some pages, query the pages,
context switch, to the new aspace, access the pages.
Basic test that the aspace abstraction is working.
Will generate errors on some of the arches that dont fully implement all
of this, but not a crash.
Kind of wasteful, but much simpler than having to manually sync every time something changes
in the kernel aspace. I think riscv machines with mmu can waste 1MB of page tables up front.
Can revisit later if needed.
When a crash is because of a BRK instruction, print that instead of
the default "unhandled synchronous exception".
Bug: 179516283
Change-Id: I9667d7157d24a79e2b2ceb7ef283ebc2b09398d0
Currently EXTRA_BUILDDEPS is evaluated before build.mk. This means that
userspace apps or other EXTRA_BUILDRULES cannot add items to
EXTRA_BUILDDEPS and have it function as would be expected.
Bug: 143636864
Change-Id: Idc1504b09f31b4c54148bb6892193d11f45e08ff
The compiler.h header defines two macros INCBIN and
INCFILE that can be used to include binary files
into C sources. This patch fixes a few issues with them:
* The .align directive is equivalent to .p2align
on some architectures (ARM/AArch64) and to .balign
on others (x86). INCBIN previously used .align and
now uses .balign for correct alignment.
* .align 1 enforces a 2-byte alignment on ARM/AArch64,
which caused the _end symbol for the binary to be off
by 1 byte in some cases, which the macro previously
accounted for (incorrectly). With the correct .balign
directive the extra byte is never added, so the size
is now correctly computed without the -1 addend.
* INCBIN should end in a .previous directive
to restore the previous section, since the macro
starts with .section.
Bug: 115420908
Change-Id: I2149e21d6f7157369a7b374a51af23933bff6b39
Up until now the bottom part of ram has been identity mapped, left over
from initial bootstrapping. Set up two top level page tables: one with the
the identity map and one without. Once the kernel starts switch to the second
but keep the former around for bootstrapping secondary cpus.
Start adding support for user address spaces, currently mostly untested.
Still have to solve the problem of keeping the kernel parts of the page tables
in sync. Will probably preallocate all of the ones needed.
Forgot to test at DEBUG=0. Both of these are basically cases where
the new DEBUG_ASSERT_COND should be used, since the default DEBUG_ASSERT
will now always emit code that gets cleaned up in the optimizer.
Pull some assert macro improvements back from zircon.
Added new variants that let you pass an arbitrary message.
Move most of the inner routine into a helper, makes for slightly
smaller codegen.
Consolidate into a single library. Also renames legacy new.h to
the more standard new.
Possible that some C++ code will need to get this added to their
MODULE_DEPS.
Move out of inline routines since the body is relatively
large and to keep the disassembly clean. Have spinlocks
store the holder cpu + 1 instead of just 1. Add an appropriate
barrier to the release.
Uses the target/debugconfig.h file pattern laid down before,
which is a bit long in the tooth but for the moment still helps
us separate target from platform.
- pull in headers for essential modules
- init clocks, gpios, uart0 out of platform_early_init
- wire up debug getc/putc to uart0
- comment out "native" uart impl
- sys/cdefs is wanted for __CONCAT()
- version.h and config_autogen.h are generated by the pico sdk
- config_autogen expects to include board file
- instead define PICO_xyz in target rules.mk
Origin: https://github.com/raspberrypi/pico-sdk
Branch: develop
Change: ebb228bfeaec81dce3b8ebdbf6c7f5fd580e2e2f
This is the contents of src/boads, src/common,
src/rp2040, and src/rp2_common, excluding cmake
goop.
I suspect we'll trim it back closer to just the
register definitions, but for now leave it mostly
as-is to simplify updating as the pico sdk updates
and we figure out how deeply (or not) to integrate
it with lk.
Use the new github actions to replace the travis-ci builders which
seem to no longer work and are being removed.
This first stab is fairly rough, just matches the explicit matrix
that was in the travis-ci hooks, but at least gets back to a buildable
state again.
If the cpu is always in thumb mode there's really no reason to pass
this switch and it can and does foul up libgcc selection.
Possible it can be removed entirely since the build system doesn't
really support anything prior to armv7 or armv6 where thumb interwork
became implicit. Unclear if it'll cause linking issues to not have it
set, however.
- just a skeleton to get us started
- cpu feature config and irq names / vectab2 setup done
- pulled in the second stage for pico as a blob for now
- seems to be hard faulting out of systick setup in platform_init()
This provides a way for a platform or target to insert code or
other secret sauce in front of the vector table for targets that
need a second stage loader prepended or something like that.
- protocol now correctly reports SWO and SWCLK clock rates on set
- remove some debug printfs that were causing fw hangs (investigate later)
- allow setting a 1MHz SWCLK rate
- CMD_ATTACH now supports an argument to select one of several special
reset or escape sequences:
ATTACH_SWD_RESET: 60 HI, 4 LO, basic line reset
ATTACH_JTAG_SWD: escape sequence for JTAG -> SWD mode switch
ATTACH_DORMANT_TO_SWD: escape squence to exit dormant mode
ATTACH_SWD_TO_DORMANT: and go back again
- add special support for writing to DP TARGETSEL register
(response phase must be ignored), needed for SWD multidrop support
- bump protocol version to 1.3
- bump firmware version to 1.0 (it's long overdue)
