In file included from lk/lib/lwip/include/lwip/netif.h:41:0,
from lk/lib/lwip/include/lwip/udp.h:40,
from lk/lib/lwip/core/dhcp.c:75:
lk/lib/lwip/core/dhcp.c: In function ‘dhcp_bind’:
lk/lib/lwip/include/ipv4/lwip/ip_addr.h:200:39: warning: the comparison will always evaluate as ‘false’ for the address of ‘gw_addr’ will never be NULL [-Waddress]
#define ip_addr_isany(addr1) ((addr1) == NULL || (addr1)->addr == IPADDR_ANY)
^
lk/lib/lwip/core/dhcp.c:987:7: note: in expansion of macro ‘ip_addr_isany’
if (ip_addr_isany(&gw_addr)) {
^
In file included from lk/lib/lwip/include/ipv4/lwip/ip.h:39:0,
from lk/lib/lwip/core/ipv4/ip.c:42:
lk/lib/lwip/core/ipv4/ip.c: In function ‘ip_input’:
lk/lib/lwip/include/ipv4/lwip/ip_addr.h:200:39: warning: the comparison will always evaluate as ‘false’ for the address of ‘current_iphdr_src’ will never be NULL [-Waddress]
#define ip_addr_isany(addr1) ((addr1) == NULL || (addr1)->addr == IPADDR_ANY)
^
lk/lib/lwip/core/ipv4/ip.c:473:24: note: in expansion of macro ‘ip_addr_isany’
if (check_ip_src && !ip_addr_isany(¤t_iphdr_src))
^
-Reduce the spinlock scope to just around the individual registered
output routine, and leave platform_dputc() call unlocked. This helps
to keep interrupts disabled for the minimum amount of time, especially
with a slow platform_dputc, at the expense of printfs being more interleaved
between cpus than before.
-The general solution to the interleaving is to use a user space mutex around
printing to any given descriptor, and handle printfing from irq-disabled state
by either not locking at all, or using a different, direct path.
If ARCH_arm_TOOLCHAIN_PREFIX isn't already set, try to use whatever is
in TOOLCHAIN_PREFIX first, before trying to use the path. This is for
compatibility with the top level makefile which currently still only
passes TOOLCHAIN_PREFIX along to the submakefiles.
Change-Id: Ib883c9c9de220df5191ee001b18c4a9eff3192c2
At the top of each irq handler, make sure PRIMASK is set to 1, so
that arch_ints_disabled(), which is now used by the spinlock code,
returns the appropriate value. On Cortex-M this is not exactly the
same thing as having irqs disabled, but it's the easiest thing to
query as long as the model of only having one level of irq handler
is maintained.
Enable fiqs at boot, and during exceptions that can trigger a
context switch.
This fixes two problems. It avoids deadlock in code that uses spinlocks
with fiqs enabled as one cpu could be holding that spinlock and get
interrupted by an fiq, while another cpu is blocked trying to lock that
spinlock with fiqs disabled. This deadlocks if the fiq is delivered to
both these cpus and the second cpu is responsible to clearing the
interrupt.
Also, since thread_preempt can return with fiqs enabled,
regrestore_short could get interrupted by an fiq which would then
corrupt elr_el1 and spsr_el1.
Change-Id: I427f39ff94514866bf87f48393d145b7f1723502
Instead of conditionalizing arch code booting secondaries, only conditionalize
waiting for each of them to come up.
This should be semi-temporary, as the need to wait will go away once arm
switches entirely to the trampoline page table strategy.
Change-Id: Idbdb9720bfac58adf514b7fa137e59aee413f4df
On some platforms, the secondary cpus have been booted and trapped by the arch/arm code
and need to be brought up lockstep to make sure the temporary page mappings are
still in place as they are booted. For these platforms, set
ARM_ARCH_BOOTS_SECONDARIES=1 to have arch_init() try to release and start the cpus.
For other platforms, after arch_init() they can simply arrange for the secondary cpus
to start themselves.
Change-Id: I7619ac66d84bd26060ddd949ae6641c1ef6e2b1d
This seems to fix some cache coherency problems with chain loading, most likely
related to the L2 cache bits in the ACTLR.
Change-Id: I0b14a71334fd1db737d6146db8745b26cfd51d97
Really to work around an arch specific problem on a particular platform, but
potentially useful elsewhere.
Change-Id: Ifae6f11cc78be8623eb0746338e18383863a4827
-have the zynq nak autobooting if the BOOT_MODE pins were set to
JTAG mode.
-Clean up some of the timeout logic a bit.
Change-Id: I4ace6354de89f2e88aa270e5ebc1bf01ebe3b046
-use lib/watchdog to manage the hardware watchdog driver
-set the default timeout to 1 second, pet at 500ms intervals
Change-Id: I04d23313083e4715791e197d4a50f319df9916aa
If a thread moved to another cpu between arm_write_ats1cpr and
arm_read_par, the pa returned will not be for the va passed in.
Change-Id: I19cbbcef09c85a7ae1d2d5122ad3f10a2282855e
Update the existing LK I2C driver interface to do a few different things.
1) Return status_t's from the driver operations, instead of just ints.
2) Add the ability to read/write multi-byte registers from I2C
devices.
3) Add a comment clarifying the use of 7-bit addresses with this API.
Also, bring existing platform implementations into line with these
changes.
Change-Id: Ie28afed28094cbab6d68266bdf37d7dc8d309366
Signed-off-by: John Grossman <johngro@google.com>
Add an architecture specific function which spins for a specific
number of CPU cycles. Currently implemented for ARM-M only.
Change-Id: Idbf2a83186cf5ffa239d644dc732fe3d419431c1
Signed-off-by: John Grossman <johngro@google.com>
+ When setting GPIOs, the MASK_DATA registers are used. Code was
properly computing which register to use based on register index
(either LSW or MSW), but was improperly computing the mask/value to
set when the GPIO to be manipulated existed in the upper 16 bits
(the shift needed to be offset by 16 bits and was not).
+ Do not manipulate things like the IO driver type, drive speed, and
so on when enabling/disabling the pullup in the SLCR registers.
Previously, whenever a GPIO was being configured, the SLCR register
was being set to be 1.8v LVCMOS, and having the DISABLE RCV bit set.
Things like the IO type have been set by the platform and should not
be manipulated by the GPIO driver. Now, the GPIO code leaves those
bits the way they were configured, and changes only the PULLUP bit
as well as the 4 levels mux bits (arguably, it should not even
change the mux bits; it is the platform's job to properly mux the
pins).
+ Address an issue with the subtle (undocumented) difference between
the DIRM and the OEN bits when configuring for input vs. output.
Please read the extensive comment in the code for details.
Change-Id: I160069eeef92b1cf0763274ccb64c5d14744f563
Signed-off-by: John Grossman <johngro@google.com>
Fix an issue with the GPIO code where it was dividing by 31 instead of
32 when attempting to map GPIO numbers to bank IDs.
Change-Id: I986eac1f9dce119445d1611666b61a7b2635ca5b
Signed-off-by: John Grossman <johngro@google.com>
Add "C++" => "CPP" translation to support libraries
having "c++" in their names, for example libstdc++.
Without such translation, resulting #define does not
compile.
Change-Id: Ieac533782a26b4ce87caf9ad2ec1105c25eeaf01
