Commit Graph

12 Commits

Author SHA1 Message Date
Travis Geiselbrecht
936ee8ac81 [arch][x86] start of an ioapic driver
Doesn't do much but provided the detection path for it and ability to
hold initialized state. The higher level platform code is going to need
to use it directly so will mostly just provide an api for access to it.

Moved ACPI sniffing back to just after the VM is initialized instead of
all the way into platform_init(). This should try to ensure that all
drivers that come up afterwards will have ioapics discovered in case
future development tries to enable and use them, kicking the machine out
of virtual-wire-mode.
2025-09-24 01:18:52 -07:00
Travis Geiselbrecht
5a520eca3e [arch][x86] start getting inter-processor-interrupts working
-Move the local apic driver to arch/x86
-Add routines to send IPIs between cpus

Something is unstable at the moment and the system crashes after a while
with random corruptions when using SMP.
2025-04-01 00:40:50 -07:00
Travis Geiselbrecht
d05bed3a25 [platform][pc] add local apic timer support
Supports deadline TSC and regular timer support.
Calibrated from the PIT if regular timer support is used.
2025-03-31 00:01:45 -07:00
Travis Geiselbrecht
2987f73d08 [platform][pc] add support for TSC based clock
-Detect if under KVM hypervisor and read tick rate or
-calibrate tick against PIT
2025-03-30 21:59:39 -07:00
Travis Geiselbrecht
09412c194f [platform][pc] refactor existing PIT code into separate file
Extend the PIT driver to allow for one shot timers even though it
monotonically runs a 1kHz tick. This allows it to keep time and provide
one shot events, though only at 1ms resolution.
2025-03-30 14:54:01 -07:00
Travis Geiselbrecht
6538baea70 WIP x86-smp
add uspace mmu support for x86-64
trampoline x86-64 cpus to long mode and into the kernel aspace
2024-12-11 00:19:57 -08:00
Travis Geiselbrecht
1afb5d7a66 WIP x86 smp: start the framework for detecting and starting secondary cores 2024-12-06 23:40:26 -08:00
Travis Geiselbrecht
fb1e414a09 [dev][bus][pci] major refactor of the PCI bus driver
-Add a bus manager level, which is an object oriented walk of the pci
busses to build a per device object for later manipulation.
-Add features to enable MSI interrupts.
-Extend generic interrupt api to allow the platform to allocate vectors
for MSI interrupts.
-Rearrange a bit of the pc platform for the platform api changes.
-Add PC platform support for using the local apic to EOI MSI vectors.
-Fix up a few existing PCI drivers for small API changes.
-Add a few stubbed out routines for non PC platforms that use PCI.
2021-12-27 22:24:31 -08:00
Travis Geiselbrecht
cba9e47987 [license] replace the longer full MIT license with a shorter one
Used scripts/replacelic. Everything seems to build fine.
2019-07-05 17:22:23 -07:00
Travis Geiselbrecht
ee672a5471 [arch][x86] flatten x86-64 and x86 into a single tree of code
Major refactor of x86 code into a single arch.
Also bump both 32 and 64 bit to running the kernel at a 'high' address.
2016-02-29 12:42:45 -08:00
Corey Tabaka
94f3f37b4a [platform][pc] Add basic UART support and connect the console to it.
This is especially useful when using the "nographic" option of qemu like this:

qemu -kernel build-pc-x86/lk.bin -nographic

Define WITH_CGA_CONSOLE=1 to enable the CGA console instead.
2012-07-02 00:35:01 -07:00
Corey Tabaka
47db8d46e4 Reorganization to better fit platform/target conventions. 2009-04-24 11:14:38 -07:00