Doesn't do much but provided the detection path for it and ability to
hold initialized state. The higher level platform code is going to need
to use it directly so will mostly just provide an api for access to it.
Moved ACPI sniffing back to just after the VM is initialized instead of
all the way into platform_init(). This should try to ensure that all
drivers that come up afterwards will have ioapics discovered in case
future development tries to enable and use them, kicking the machine out
of virtual-wire-mode.
Extend the PIT driver to allow for one shot timers even though it
monotonically runs a 1kHz tick. This allows it to keep time and provide
one shot events, though only at 1ms resolution.
Use the legacy version of the memory sizing info that just hands the
kernel 2 implicit ranges: 0 ... X and 1MB ... Y.
Not ideal, but when booting on very old machines without BIOS e820 call
implemented it's all you got.
Move the mmu_initial_mapping from platform into arch/x86. For this
architecture the default mappings are basically hard coded in arch/x86
anyway, so move ownership of this data there, closer to where it's
actually initialized.
Update the 32 and 64bit paging code to properly use the paddr_to_kvaddr
and vice versa routines.
Update to allocate page tables directly from the pmm instead of the heap
(on 32bit code).
The old method assumed that all of the tables were mapped within the
kmap area of the kernel. This basically works on 64bit machines but on a
32bit x86 its entirely likely the ACPI tables are at higher physical
addresses that can be reached, which is currently limited to 1GB.
By using the VM it means it can individually map the headers and each
individual table.
Parse up to 16 pmm arenas from the multiboot memory data structure. Roll
the 32bit code to properly trim at 1GB as before, but using new logic.
Remove conditional checks on WITH_KERNEL_VM in x86 code, which only
really compiles with the mmu and the vm on.
Wire them up on arm and riscv which need them. x86-pc does not, so dont
call it.
Also fix a few miscellaneous bugs, notably PCI not detecting 64bit bars
properly due to an off by one bit error.
-Add a bus manager level, which is an object oriented walk of the pci
busses to build a per device object for later manipulation.
-Add features to enable MSI interrupts.
-Extend generic interrupt api to allow the platform to allocate vectors
for MSI interrupts.
-Rearrange a bit of the pc platform for the platform api changes.
-Add PC platform support for using the local apic to EOI MSI vectors.
-Fix up a few existing PCI drivers for small API changes.
-Add a few stubbed out routines for non PC platforms that use PCI.
Almost nothing changes here except moving braces to the same line as the
function declaration. Everything else is largely whitespace changes and
a few dangling files with tab indents.
See scripts/codestyle
Add bogus _end_of_ram to the x86|x86-64 linker script to satisfy the
heap's initial setup of it. _heap_end is still manipulated in platform
space to reflect the real memory map.
-Remove top level DEBUG=<N> define
-Rename DEBUGLEVEL to LK_DEBUGLEVEL to be clear.
-Fix the places that used DEBUGLEVEL and the few spots that #ifdef
on DEBUG.
This is especially useful when using the "nographic" option of qemu like this:
qemu -kernel build-pc-x86/lk.bin -nographic
Define WITH_CGA_CONSOLE=1 to enable the CGA console instead.
