Commit Graph

9 Commits

Author SHA1 Message Date
Travis Geiselbrecht
e03d4196a3 [platform][halt] refactor the default halt/reboot/shutdown logic
Move common logic into a default routine in platform/power that other
platforms can reuse to implement the general default shutdown logic.
Add helper routines to print the cause.
Refactor the platforms that had substantial halt logic to reuse the
default implementation.
2024-08-09 19:30:20 -07:00
Travis Geiselbrecht
d39f2db58d [platform][device-tree] fix up 3 platforms to use the new fdtwalk routines
Three platforms had basically duplicated logic that just was pulled into
the fdtwalk library. Fix these up to call into those routines instead.

-qemu-virt-arm
-qemu-virt-riscv
-jh7110 (visionfive 2 soc)
2024-04-16 23:15:00 -07:00
Travis Geiselbrecht
03eb343e52 [arch][riscv] add a way for platforms to set optional riscv ISA extensions
A pretty simple mechanism, a list of extensions added to
RISCV_EXTENSION_LIST make variable is expanded to an underscore
delimited string appended to the end of -march=

Pretty simple but it should work for now.
2024-04-07 23:10:31 -07:00
Travis Geiselbrecht
00b06a8302 [arch][riscv] change secondary cpu bootstrap api
Instead of setting a counter of the number of secondaries to start, have
platform or target code pass in a list of harts to start instead. This
allows for there to be discontinuties in the layout of the cpu harts, or
in the case of some sifive based hardware, hart 0 is otherwise offline.
2024-04-07 22:32:49 -07:00
Travis Geiselbrecht
d9b7d070c9 [top] add header declaration for lk_boot_args
Update users of the boot args array to use the header.
2024-02-11 00:38:09 -08:00
Travis Geiselbrecht
58fd2c36d5 [platform][jh7110] Tweak logic to find the FDT from the uimage 2023-10-15 14:41:30 -07:00
Travis Geiselbrecht
a1eb850079 [target][visionfive2] set the time base properly
Seems to be running at 4Mhz according to the device tree.
2023-03-09 23:20:18 -08:00
Travis Geiselbrecht
7c2c8d8e56 [dev][interrupt][riscv_plic] merge now 3 implementations of the same plic driver into one
Move a copy of the PLIC driver out of one of the platforms and make the
setup of the interrupt controller a bit more dynamic.
2023-03-09 23:09:32 -08:00
Travis Geiselbrecht
c66ad44efa WIP [target][visionfive2] Add initial support for a VisionFive 2 RISC-V board
Still TODO:
-Set the timer rate properly
-Fix nonzero based hart secondary cpu boot
-Try to parse the device tree for some information
2023-03-06 01:06:27 -08:00