Commit Graph

10 Commits

Author SHA1 Message Date
Travis Geiselbrecht
b7d69d8804 [arch][x86] handle the local apic of the boot cpu not being 0
I have a bulldozer machine here that curiously starts the APIC IDs for
the cpus at 16 and counts up.

This is a problem since the current code assumes that the boot cpu is 0,
and would try to start itself (apic id 16) later because it thought it
was the first secondary. Fix this by re-reading the APIC id on the boot
cpu and patching the percpu structure a bit into boot. Kinda a hack but
avoids having to detect the APIC, find the type of ID to read, etc.

Also means that practically speaking the system is using the full 32bit
APIC IDs if that feature is present, since now the local apic id is
entirely read from the local apic as it should be (if present).

Fixes #475
2025-09-22 20:57:30 -07:00
Travis Geiselbrecht
bdf2203fdc [arch][x86][lapic] a little bit of restructuring of some recent lapic code
Functionally equivalent, but refactor two copies of local apic
initialization code into a shared routine.
2025-09-21 21:53:35 -07:00
little fairy
d0eb5c464e [arch][x86] Read full 32bit apic id from x2apic msr if available (#465) 2025-09-21 21:04:00 -07:00
Travis Geiselbrecht
71e795de19 [arch][x86] get SMP working on x86-32
- Added very basic user page table support (needed to bootstrap the
  secondary cpus)
- Added MP bootup code for 32bit.
2025-04-06 19:09:32 -07:00
Travis Geiselbrecht
5a520eca3e [arch][x86] start getting inter-processor-interrupts working
-Move the local apic driver to arch/x86
-Add routines to send IPIs between cpus

Something is unstable at the moment and the system crashes after a while
with random corruptions when using SMP.
2025-04-01 00:40:50 -07:00
Travis Geiselbrecht
6b89609887 WIP x86-64 SMP: get the 64bit secondaries fully started
Rearrange some of the cpu initialization code to be runnable on each cpu
as they come up. Complete the 64bit bootstrap mechanism and call into C
code.

Makes it as far as trying to reschedule via an IPI. Need to implement
local apic based IPI mechanism.
2024-12-13 00:21:16 -08:00
Travis Geiselbrecht
1afb5d7a66 WIP x86 smp: start the framework for detecting and starting secondary cores 2024-12-06 23:40:26 -08:00
Travis Geiselbrecht
181796e843 WIP x86 get x86-32 working with a per-cpu gs: segment register for the kernel 2024-12-06 22:30:48 -08:00
Travis Geiselbrecht
902e2fcb8a WIP set up per cpu structures for x86-64
only on the boot cpu for now
2024-12-06 21:11:51 -08:00
Travis Geiselbrecht
fd79fccdde WIP x86 SMP 2024-12-06 00:03:48 -08:00