Commit Graph

16 Commits

Author SHA1 Message Date
Travis Geiselbrecht
b7d69d8804 [arch][x86] handle the local apic of the boot cpu not being 0
I have a bulldozer machine here that curiously starts the APIC IDs for
the cpus at 16 and counts up.

This is a problem since the current code assumes that the boot cpu is 0,
and would try to start itself (apic id 16) later because it thought it
was the first secondary. Fix this by re-reading the APIC id on the boot
cpu and patching the percpu structure a bit into boot. Kinda a hack but
avoids having to detect the APIC, find the type of ID to read, etc.

Also means that practically speaking the system is using the full 32bit
APIC IDs if that feature is present, since now the local apic id is
entirely read from the local apic as it should be (if present).

Fixes #475
2025-09-22 20:57:30 -07:00
Travis Geiselbrecht
bdf2203fdc [arch][x86][lapic] a little bit of restructuring of some recent lapic code
Functionally equivalent, but refactor two copies of local apic
initialization code into a shared routine.
2025-09-21 21:53:35 -07:00
Travis Geiselbrecht
0ac0911404 [arch][x86] save the translated kernel pgdir physical address
This keeps from needing to recompute it on every context switch back to
the kernel aspace.
2025-04-13 22:43:28 -07:00
Travis Geiselbrecht
e970a6ea4b [arch][x86-64] remove extra segment register set in start.S 2025-04-10 22:25:38 -07:00
Travis Geiselbrecht
6b89609887 WIP x86-64 SMP: get the 64bit secondaries fully started
Rearrange some of the cpu initialization code to be runnable on each cpu
as they come up. Complete the 64bit bootstrap mechanism and call into C
code.

Makes it as far as trying to reschedule via an IPI. Need to implement
local apic based IPI mechanism.
2024-12-13 00:21:16 -08:00
Travis Geiselbrecht
6538baea70 WIP x86-smp
add uspace mmu support for x86-64
trampoline x86-64 cpus to long mode and into the kernel aspace
2024-12-11 00:19:57 -08:00
Travis Geiselbrecht
fd79fccdde WIP x86 SMP 2024-12-06 00:03:48 -08:00
Alex Richardson
c2a31bf8a6 [x86][clang] Make return mnemonic compatible with clang
GCC appears to accept the Intel retf syntax in AT&T mode but clang is
stricter and requires use of lret.
2023-06-07 15:55:50 -07:00
Travis Geiselbrecht
7742bd021b [arch][x86] general cleanup
Clean up the x86.h file a bit with how constants are defined
Switch rdtsc to builtin
Added all of the known bits for the main CR registers.
Move the invlpg macro over to the common header.
Update comments in start.S
2022-11-02 23:02:24 -07:00
Travis Geiselbrecht
62e2e7dba0 [platform][pc] move the multiboot header into generic space
Share the header with arch/x86 code
Clean up the use of the boot flags
Add code to print the framebuffer information, if present
2022-08-07 23:04:23 -07:00
Travis Geiselbrecht
f7d8e2300c [warnings] add -Wshadow which helps detect local variables that override globals
Nothing particularly bad showed up but cleaned up a bit of code.
2020-07-25 16:49:25 -07:00
Travis Geiselbrecht
cba9e47987 [license] replace the longer full MIT license with a shorter one
Used scripts/replacelic. Everything seems to build fine.
2019-07-05 17:22:23 -07:00
Travis Geiselbrecht
1b7a28efb8 [include][lk] fixup lk/ include path move 2019-06-19 19:46:11 -07:00
klemens
d0b90c2d68 [spelling] spelling-fixes. (not external/) 2016-08-25 17:30:34 -07:00
Zhu, Bing
68447dbeca [arch][x86] load initial stack pointer in boot entry
Initially, stack pointer (esp) is undefined in multiboot protocol,
to avoid potential memory corruption, set it with defined value.

Signed-off-by: Zhu, Bing <bing.zhu@intel.com>
2016-03-15 10:24:14 -07:00
Travis Geiselbrecht
ee672a5471 [arch][x86] flatten x86-64 and x86 into a single tree of code
Major refactor of x86 code into a single arch.
Also bump both 32 and 64 bit to running the kernel at a 'high' address.
2016-02-29 12:42:45 -08:00