Was always this way for some reason, which would tend to print the
calling routine that called the routine that paniced, which was of
dubious use. Simplify the panic logic and just call it as a standard
varargs routine.
No real change except moving fdt walking code into the fdtwalk library.
Also update some constants for ARM virt and bump the load address to
make sure the FDT works. Turns out it had been missing for a while so it
was actually not finding it because the kernel was loaded too close to
the start of memory.
Only tested with SBI and supervisor mode, but that's all I have now.
Add checked in copies of the device tree needed for a uboot uimage
needed to start it.
Add a define that sets the maximum allowed hart number, potentially
higher than the maximum number of allowed cpus.
This lets us more cleanly deal with having a higher HART number than the
logical cpu numbering. Only really works where it's still fairly packed
around 0, but in the case of the Sifive Unleased board it's just offset
by 1 so it's not a huge loss.
Generally clean up RISCV SMP boot code by rearranging things a bit as
well.
Set -fno-builtin to keep the compiler from generating load/stores using
sse outside of floating point code. Not ideal for a lot of reasons but
it's difficult to segregate kernel code and user code such that it only
generates SSE instructions there.
Will probably need to do some work to let certain flags be set per
module, and then have only some of the modules be marked as user vs
kernel.
-Fix plic driver to handle machine vs supervisor mode
-Add switch to scripts/do-qemuriscv to run in supervisor mode (with OpenSBI)
-Use the FDT to detect the number of cpus and size of memory
For one of the riscv embedded targets, the clock ticks at such a slow
rate that the compiler will warn of a div by zero. Add a compile time
hack for this.
Add support for running LK in supervisor mode or machine mode.
- Macro-ify CSR access to use correct CSR # or use SBI call as req'd
- Add support to make SBI calls
- Split CLINT and lk timer abstraction so that RISC-V timer can use SBI
as required.
- Add support for booting other harts as primary since hart0 on U540
does not support S-mode. A map is used to get LK cpu number from
hartid.
Support mp lk start on RISC-V. Several changes throughout were required:
- Add signal in asm start to force secondary harts to wait for bss to be
cleared.
- Use mhartid in arch_curr_cpu_num, PLIC, and CLINT
- Use tp register as thread pointer instead of global variable.
- Support sending IPIs between harts using CLINT
- Add spinlock implementation
Most of changes were moving around where macros were defined, plus the
following:
- Remove requirement for floating point on RV64 to support booting
monitor core on U54 SoC.
- Add support for Debug LEDs on HiFive Unleashed Board
* Adds target tms570-launchpad, for TI TMS570 Launchpad Dev Kit
(https://www.ti.com/store/ti/en/p/product/?p=LAUNCHXL2-TMS57012)
* Adds CPU definitions for Cortex R4F (BE) CPU, implementing
ARMv7-R ISA. Does not yet add definitions for ARMv7 arch entry
functions.
* Board does not yet build - platform.c/uart.c are empty, no GIC
entry points provided.
Tweak the novm allocator to let us more easily add a variable sized
arena at boot.
Also added code to trap secondary cpus and reenable the use of WFI
instruction.
Very little needed to port except to conditionalize some assembly in the
context switch and exception code. Mostly needed to move build system
stuff around and add a new project.
The virt machine is a generic target, much like the arm virt machine.
Intended to be simple to use and a good target to run large systems like
linux on. At the moment simply support booting and simple uart and timer
support.
Fixes a race in the STM USB driver which can lead to the device seeing
only 0-length SETUP transfers. The bug ultimately leads to a failed
USB enumeration. The race condition is described in further detail
below.
The current behavior of the IRQ handler for received OUT transfers is
as such:
- Clear RX_CTR bit (at this point, HW sees that SW has acknowledged
previous SETUP/OUT transfer, and the HW will now accept new STATUS
transfers)
- Call out to the client OutStageCallback (nothing significant here)
- Set EP_RX_CNT back to size of max_packet (was previously set to 0 as
we expect to receive 0-length OUT transfer from host. HW uses this
value to limit the amount of data it can receive)
- Set RX_STAT back to VALID (the HW can now receive new STATUS/OUT
transfers)
The important thing to note here is that even before RX_STAT is set to
VALID in the last step, the HW can still receive and process a new
SETUP transfer as long as RX_CTR is cleared (the spec has some detail
about this under section "Control Transfers" on page 867:
https://www.st.com/resource/en/reference_manual/dm00031936.pdf). The
race will occur if we receive a SETUP transfer after clearing RX_CTR
but before adjusting EP_RX_CNT back to max_packet. In this case, the
IRQ handler will run for the newly received SETUP transfer, but the
transfer will have no data associated with it (the driver ends up
using the previous transfer data which was cached).
We can eliminate the race window by waiting to clear RX_CTR only after
we've reset EP_RX_CNT. In this case the HW will ignore any new SETUP
transfers until after the EP_RX_CNT is reset back to the desired
value.
TL;DR most uses of lib/console.h -> lk/console_cmd.h
Move the part that lets a piece of code somewhere in the system to
define a console command from the actual lib/console api to start an
instance of the console. Move in almost every place the user of the
console command definition to the new header, lk/console_cmd.h which is
always in the include path.
Also remove most uses of testing for WITH_LIB_CONSOLE since you can
almost always just safely define it and then let the linker remove it.
Examples are include/platform.h -> platform/include/platform.h
include/target.h -> target/include/target.h
The old model generally considered these to be Always There includes,
but they're starting to stick out more and more so may as well actually
follow the model that most of the rest of the system follows.
