Commit Graph

2189 Commits

Author SHA1 Message Date
Andrei Homescu
7e502816f6 [include][compiler.h] Fix INCBIN/INCFILE macros
The compiler.h header defines two macros INCBIN and
INCFILE that can be used to include binary files
into C sources. This patch fixes a few issues with them:
* The .align directive is equivalent to .p2align
  on some architectures (ARM/AArch64) and to .balign
  on others (x86). INCBIN previously used .align and
  now uses .balign for correct alignment.
* .align 1 enforces a 2-byte alignment on ARM/AArch64,
  which caused the _end symbol for the binary to be off
  by 1 byte in some cases, which the macro previously
  accounted for (incorrectly). With the correct .balign
  directive the extra byte is never added, so the size
  is now correctly computed without the -1 addend.
* INCBIN should end in a .previous directive
  to restore the previous section, since the macro
  starts with .section.

Bug: 115420908
Change-Id: I2149e21d6f7157369a7b374a51af23933bff6b39
2021-04-08 23:55:27 -07:00
Travis Geiselbrecht
f463f50e54 [arch][riscv] add trampoline page table and start user space address space support
Up until now the bottom part of ram has been identity mapped, left over
from initial bootstrapping. Set up two top level page tables: one with the
the identity map and one without. Once the kernel starts switch to the second
but keep the former around for bootstrapping secondary cpus.

Start adding support for user address spaces, currently mostly untested.

Still have to solve the problem of keeping the kernel parts of the page tables
in sync. Will probably preallocate all of the ones needed.
2021-04-03 02:40:32 -07:00
Travis Geiselbrecht
5a3d51e3e7 [assert] fix up a few places broken at DEBUG=0 after recent assert changes
Forgot to test at DEBUG=0. Both of these are basically cases where
the new DEBUG_ASSERT_COND should be used, since the default DEBUG_ASSERT
will now always emit code that gets cleaned up in the optimizer.
2021-04-02 20:16:53 -07:00
Travis Geiselbrecht
897240eb43 [lib][unittest] more improvements from zircon
Have the msg argument be optional in C++.
2021-04-02 19:28:58 -07:00
Travis Geiselbrecht
9a796e868a [assert] update the assert macros
Pull some assert macro improvements back from zircon.

Added new variants that let you pass an arbitrary message.
Move most of the inner routine into a helper, makes for slightly
smaller codegen.
2021-04-02 19:28:58 -07:00
Travis Geiselbrecht
461ecbb677 [make][cpp] bump cpp revision to C++14
Shouldn't be a large problem, since it's been standard in gcc and clang
for quite a few years at this point.
2021-04-02 19:28:58 -07:00
Travis Geiselbrecht
ebdc1ea077 [lib][libcpp] move c++ specific shims out of libc and heap
Consolidate into a single library. Also renames legacy new.h to
the more standard new.

Possible that some C++ code will need to get this added to their
MODULE_DEPS.
2021-04-02 19:28:58 -07:00
Travis Geiselbrecht
890504c922 [inc][compiler] update compiler.h with new bits from zircon
Mostly macros dealing with clang, which do not yet work, but lets
some other zircon code be compiled cleanly.
2021-04-02 19:28:58 -07:00
Travis Geiselbrecht
c5ef3165e4 [libc] add LLONG_* to limits.h 2021-04-02 19:28:58 -07:00
Travis Geiselbrecht
d28e8dc3e0 [kernel][mutex] tweak a mutex routine to take a const 2021-04-02 19:28:58 -07:00
Michael Bishop
41f651268b [libc] allow arch string rules to be missing
[elf] add the constant for VC4
2021-04-01 21:34:29 -07:00
Travis Geiselbrecht
1db813d2f6 [arch][riscv] spiff up the spinlock code a bit
Move out of inline routines since the body is relatively
large and to keep the disassembly clean. Have spinlocks
store the holder cpu + 1 instead of just 1. Add an appropriate
barrier to the release.
2021-03-30 02:48:59 -07:00
Travis Geiselbrecht
3be4698671 [arch][test] add a new unittest for the arch mmu code
Just a skeleton at the moment, simply creates an arch aspace
and destroys it.
2021-03-30 02:48:59 -07:00
Travis Geiselbrecht
7102838b49 [arch] have each arch define ARCH_HAS_MMU
This lets some code decide whether or not there's any mmu
present to use. Also kernel VM will complain if it isn't set
as an extra safety.
2021-03-30 02:48:59 -07:00
Travis Geiselbrecht
45a27cbf14 [arch][riscv] more work on riscv MMU code
Use a callback based shared walker to implement the
same page table walking code for different operations.

Add SBI hooks for TLB flushing.
2021-03-30 02:48:59 -07:00
Travis Geiselbrecht
c6d8476adb [arch][riscv] rename mmu.c -> mmu.cpp
Going to try an idea with the page table code that requires C++.

If it works out, I'll keep this commit.
2021-03-30 02:48:59 -07:00
Travis Geiselbrecht
e3a43bb899 [lib][unittest] spiff up the unittest lib
Roll some improvements back from zircon kernel.
2021-03-30 02:48:59 -07:00
Travis Geiselbrecht
6ea5645ca3 [arch][riscv] stub out arch_enter_uspace for riscv
Copied implementation from ARM and then stubbed it out.
2021-03-29 03:04:12 -07:00
Travis Geiselbrecht
a319a1f68d [target][pico][ci] add pico-test to the build matrix 2021-02-15 21:07:00 -08:00
Travis Geiselbrecht
c8e4a56f00 [target][pico] switch the uart config to target driven
Uses the target/debugconfig.h file pattern laid down before,
which is a bit long in the tooth but for the moment still helps
us separate target from platform.
2021-02-15 21:06:05 -08:00
Travis Geiselbrecht
a0f34be4ec [project][pico-test] inherit all of the tests from the virtual test project 2021-02-15 21:06:05 -08:00
Travis Geiselbrecht
7217848f45 [arch][arm-m] dont set up unused vectors on armv6m cores
Just saves a few hundred bytes of unused code.
2021-02-15 21:06:05 -08:00
Travis Geiselbrecht
c2574c46c6 [arch][arm-m] add logic to conditionally set VTOR if present
VTOR is optional on cortex-m0+, so let the platform or target set
a define to do it.

Move the RP20xx platform to this switch.
2021-02-15 21:06:05 -08:00
Brian Swetland
7d3f648e88 [rp20xx] quick and dirty early init using pico-sdk driver code
- pull in headers for essential modules
- init clocks, gpios, uart0 out of platform_early_init
- wire up debug getc/putc to uart0
- comment out "native" uart impl
2021-02-15 21:06:05 -08:00
Brian Swetland
9c769f6931 [rp20xx][pico-sdk] add some missing / generated headers
- sys/cdefs is wanted for __CONCAT()
- version.h and config_autogen.h are generated by the pico sdk
- config_autogen expects to include board file
- instead define PICO_xyz in target rules.mk
2021-02-15 21:06:05 -08:00
Brian Swetland
e65436dca9 [external][pico] import source from rpi pico sdk
Origin: https://github.com/raspberrypi/pico-sdk
Branch: develop
Change: ebb228bfeaec81dce3b8ebdbf6c7f5fd580e2e2f

This is the contents of src/boads, src/common,
src/rp2040, and src/rp2_common, excluding cmake
goop.

I suspect we'll trim it back closer to just the
register definitions, but for now leave it mostly
as-is to simplify updating as the pico sdk updates
and we figure out how deeply (or not) to integrate
it with lk.
2021-02-15 21:06:05 -08:00
Travis Geiselbrecht
b730a5ef5c [github][actions] Add a new action to build LK, replacing travis-ci
Use the new github actions to replace the travis-ci builders which
seem to no longer work and are being removed.

This first stab is fairly rough, just matches the explicit matrix
that was in the travis-ci hooks, but at least gets back to a buildable
state again.
2021-02-14 20:23:39 -08:00
Travis Geiselbrecht
7b0ca3c984 [make] print debug level on build 2021-02-14 20:08:35 -08:00
Brian Swetland
5434847c51 [libc] C style static_assert takes two arguments
Fix this up and fix up the one existening dependency on the
existing incorrect behaviour.
2021-02-06 20:30:34 -08:00
Travis Geiselbrecht
e231864e12 [arch][arm-m] disable -mthumb-interwork for cortex-m targets
If the cpu is always in thumb mode there's really no reason to pass
this switch and it can and does foul up libgcc selection.

Possible it can be removed entirely since the build system doesn't
really support anything prior to armv7 or armv6 where thumb interwork
became implicit. Unclear if it'll cause linking issues to not have it
set, however.
2021-02-06 17:32:13 -08:00
Travis Geiselbrecht
7c43f66169 [platform][pi20xx] Add a tool to convert the final .bin file to a UF2 file
Tool is MIT licensed, taken from
https://github.com/microsoft/uf2
2021-02-06 16:29:02 -08:00
Brian Swetland
b142c6bdcd [rp20xx][pico] platform and target for rp20xx and pico board
- just a skeleton to get us started
- cpu feature config and irq names / vectab2 setup done
- pulled in the second stage for pico as a blob for now
- seems to be hard faulting out of systick setup in platform_init()
2021-02-05 19:25:19 -08:00
Brian Swetland
9270460385 [arm][cm][linkscripts] add a "secondstage" section
This provides a way for a platform or target to insert code or
other secret sauce in front of the vector table for targets that
need a second stage loader prepended or something like that.
2021-02-05 16:59:12 -08:00
Brian Swetland
6e3edb87de [app][mdebug] version 1.0
- protocol now correctly reports SWO and SWCLK clock rates on set
- remove some debug printfs that were causing fw hangs (investigate later)
- allow setting a 1MHz SWCLK rate
- CMD_ATTACH now supports an argument to select one of several special
  reset or escape sequences:
  ATTACH_SWD_RESET: 60 HI, 4 LO, basic line reset
  ATTACH_JTAG_SWD: escape sequence for JTAG -> SWD mode switch
  ATTACH_DORMANT_TO_SWD: escape squence to exit dormant mode
  ATTACH_SWD_TO_DORMANT: and go back again
- add special support for writing to DP TARGETSEL register
  (response phase must be ignored), needed for SWD multidrop support
- bump protocol version to 1.3
- bump firmware version to 1.0 (it's long overdue)
2021-02-01 17:46:33 -08:00
Brian Swetland
16ba667296 [app][mdebug] makefile.fw and linkscript to regenerate fw
The original tooling is lost to the mists of time and long-discarded
workstations, but this generates identical results and will enable
updating the code on the m0 sub-processor going forward.  Yay.
2021-01-30 02:51:41 -08:00
Brian Swetland
98cf1e5067 [app][mdebug] normalize whitespace in fw-m0sub.h
The xxd tool generates two spaces of indent, not four.

Fix this existing file to match the tool output to make it easier
to detect changes to the resulting image header when rebuilt.
2021-01-30 02:48:34 -08:00
Piotr Tworek
a969cc9c99 [libc] Fix UINT16_MAX, INT16_MIN and INT16_MAX definitions.
The defines from limits.h have SHRT, not SHORT in their names.
2021-01-25 18:49:35 -08:00
Travis Geiselbrecht
c55ab00668 [platform][sifive] add a GPIO driver and switch the target setup to it 2021-01-20 01:11:29 -08:00
Travis Geiselbrecht
7033559d38 [inc][c++] add some additional __BEGIN_CDECL/__END_CDECLS to various global headers
Just a few that were missed, and picked up with some additional C++ code.
2021-01-20 01:02:48 -08:00
Travis Geiselbrecht
3083f63253 [arch][riscv] fix accidental file rename in last commit
Have been fiddling with using some C++ in the riscv code, but didn't
intend to check this file rename in yet.
2021-01-14 20:21:22 -08:00
Travis Geiselbrecht
649ca7dd54 [make] encode the source file extension into the .o file
Instead of compiling each .c or .cpp or .S file into an equivalent .o file,
map it to a file with .c.o or .cpp.o extension.

IE,
    foo.c -> foo.c.o
    bar.cpp -> bar.cpp.o

Reason for this being that if you change the suffix of a file it'll
automatically pick it up and recompile.
2021-01-14 18:43:18 -08:00
Travis Geiselbrecht
b655fea02f [platform][qemu-virt-riscv] switch to dlmalloc as default heap
miniheap is really not set up for large memory machines.
2021-01-14 18:27:37 -08:00
Travis Geiselbrecht
6f5fe1efca [arch][riscv] add proper SBI extension support
-Add support for probing SBI extensions
-Switch to newer versions if present
-Add HBM extension which allows proper secondary cpu bootstrap
-Add support for secondary bootup via HBM.
2020-12-30 03:43:54 -08:00
Travis Geiselbrecht
d1c04827e9 [arch][riscv] make sure zero sized bsses work
-Skip looping if the bss size is actually zero

Issue #288
2020-12-30 02:15:26 -08:00
Travis Geiselbrecht
6bd5e9e857 [arch][riscv] tweak some of the start.S code that was recently modified
-Add a comment as to why a2 is used to hold the assigned cpu id
-Add a memory fence after releasing the secondary cpus
2020-12-30 02:02:50 -08:00
Travis Geiselbrecht
a21bc34022 [arch][riscv] restructure the qemu starter script to share the embedded and non embedded logic 2020-12-30 02:02:42 -08:00
Travis Geiselbrecht
6ea6256d89 [platform][sifive] add switch to scripts/do-riscvqemu to run sifive unleashed
Also fix up some broken bits on the previously unused qemu-sifive-u target.
2020-12-30 01:40:05 -08:00
Travis Geiselbrecht
1e50428091 [arch][riscv] remove the last of the RISCV_BOOT_HART mechanism
Now the harts are dynamically numbered, so don't need
this mechanism anymore.
2020-12-30 01:09:24 -08:00
Travis Geiselbrecht
c2d77234c3 [arch][riscv] switch to using a boot lottery to dynamically assign cpu number
Turns out that in some cases we can't really rely on a particular boot cpu id
so go ahead and simply dynamically assign cpu numbers by having each cpu
increment an atomic number in the very top of start.S. The first one in gets
the worm.
2020-12-30 00:52:41 -08:00
Travis Geiselbrecht
431543a9bf [platform][qemu-virt-arm] spiff up the PSCI call to boot the secondary cpus
Add a few comments and print something in case of error.
2020-12-17 01:40:40 -08:00