Commit Graph

18 Commits

Author SHA1 Message Date
Travis Geiselbrecht
7c2c8d8e56 [dev][interrupt][riscv_plic] merge now 3 implementations of the same plic driver into one
Move a copy of the PLIC driver out of one of the platforms and make the
setup of the interrupt controller a bit more dynamic.
2023-03-09 23:09:32 -08:00
Travis Geiselbrecht
91d0a5f7d1 [lib][fdtwalk] add routine to find and parse /reserved-memory node
Add logic to the riscv virt platform to properly mark off memory
claimed by OpenSBI.
2022-12-17 17:12:35 -08:00
Travis Geiselbrecht
2d561b4fcf [platform][qemu-virt-riscv] seems the first 512K are now used by opensbi 1.1
Looks like this is described in /reserved_memory/mmode_resv@<address> as
patched by opensbi on top of the existing qemu provided dtb.

Future patch should parse this instead of hard coding it.
2022-12-17 00:57:37 -08:00
Travis Geiselbrecht
095aca80f1 [arch][riscv][sbi] add the pmu extension, tweak boot messages, qemu-virt use reset calls 2022-05-29 14:48:04 -07:00
Travis Geiselbrecht
fe28bd8a95 [lib][minip] add a mechanism to wait for the stack to be configured
Configured in this case means an ip address assigned and a nic
installed.
2022-03-19 14:46:01 -07:00
Travis Geiselbrecht
f1431b81d0 [bus][pci] Support for dynamically assigning BARs and bridges if needed
In the case of platforms where a bios or firmware has not already
assigned all the resources, do so. Requires the platform supply one or
more ranges of physical address space and IO that can be mapped into
BARs.

Handles iterating through bridges, computing the sizes of all the
peripherals downstream and rolling that up as well.
2022-02-06 19:46:39 -08:00
Travis Geiselbrecht
36e73e0fac [bus][pci] add routines to pass in PCI bus resources prior to starting the pci bus manager
Wire them up on arm and riscv which need them. x86-pc does not, so dont
call it.

Also fix a few miscellaneous bugs, notably PCI not detecting 64bit bars
properly due to an off by one bit error.
2022-02-06 19:46:39 -08:00
Travis Geiselbrecht
06ab680159 [lib][fdtwalk] add support to return the io/mmio pci aperture as well
FDT encodes the range of available mmio and io ports that the PCI bus
can use to map bars. Return this information out of the FDT walker
helper routines to feed into the PCI bus manager in the future.
2022-02-06 19:46:39 -08:00
Travis Geiselbrecht
c9eae714db [platform][qemu-virt-riscv] pick the PCIE ecam out of FDT and initialize PCI bus 2021-11-12 21:23:09 -08:00
Travis Geiselbrecht
f463f50e54 [arch][riscv] add trampoline page table and start user space address space support
Up until now the bottom part of ram has been identity mapped, left over
from initial bootstrapping. Set up two top level page tables: one with the
the identity map and one without. Once the kernel starts switch to the second
but keep the former around for bootstrapping secondary cpus.

Start adding support for user address spaces, currently mostly untested.

Still have to solve the problem of keeping the kernel parts of the page tables
in sync. Will probably preallocate all of the ones needed.
2021-04-03 02:40:32 -07:00
Travis Geiselbrecht
6f5fe1efca [arch][riscv] add proper SBI extension support
-Add support for probing SBI extensions
-Switch to newer versions if present
-Add HBM extension which allows proper secondary cpu bootstrap
-Add support for secondary bootup via HBM.
2020-12-30 03:43:54 -08:00
Travis Geiselbrecht
54955fb7f7 [platform][qemu-riscv] add simple hard coded support for poweroff and reset
Writing to a particular address will tell qemu to poweroff or reset.
2020-11-12 03:05:41 -08:00
Travis Geiselbrecht
7c9906a5ff [arch][riscv] Initial implementation of MMU for RISC-V
Implements both SV39 and SV48. No 32bit support yet.

Currently implements basic setup of paging in start.S by mapping a large
chunk of memory into both an identity map and to the bottom of the
kernel address space. Run the kernel out of this physical mapping.

Added basic arch mmu support for querying existing paging structures and
mapping 4K pages. No unmap support as of yet.

System boots with mmu on when running supervisor test on qemu. Untested
on real hardware as of yet.
2020-05-10 17:09:48 -07:00
Travis Geiselbrecht
89cdb26d5b [platform][arm/riscv][virt] update both arm-virt and riscv-virt to use libfdtwalk
No real change except moving fdt walking code into the fdtwalk library.

Also update some constants for ARM virt and bump the load address to
make sure the FDT works. Turns out it had been missing for a while so it
was actually not finding it because the kernel was loaded too close to
the start of memory.
2020-04-25 18:46:57 -07:00
Travis Geiselbrecht
7648ca09d9 [platform][qemu-riscv] add virtio to bring it up to par with arm virt machine 2020-01-19 16:17:34 -08:00
Travis Geiselbrecht
9c71a0ec57 [platform][qemu-riscv] Fixup qemu-riscv target
-Fix plic driver to handle machine vs supervisor mode
-Add switch to scripts/do-qemuriscv to run in supervisor mode (with OpenSBI)
-Use the FDT to detect the number of cpus and size of memory
2020-01-19 14:48:25 -08:00
Travis Geiselbrecht
bff17f7e99 [platform][riscv] add code to read the size of memory from the FDT
Tweak the novm allocator to let us more easily add a variable sized
arena at boot.

Also added code to trap secondary cpus and reenable the use of WFI
instruction.
2019-11-02 18:13:02 -07:00
Travis Geiselbrecht
ae5200595c [platform][riscv-virt] added support for QEMU's riscv 'virt' machine
The virt machine is a generic target, much like the arm virt machine.
Intended to be simple to use and a good target to run large systems like
linux on. At the moment simply support booting and simple uart and timer
support.
2019-11-02 14:19:36 -07:00