Mostly deduplicating x86-32 and x86-64 code since virtually all of it
can be shared.
Fixed up some cpuid usage which was not properly marking registers as
clobber.
From looking at the dissassembly the compiler wasn't doing a good job
with the overly complicated version shared with the larger arm cores.
Simplify it by recognizing that you can save the state directly from
PRIMASK and restore it more simply.
This lets some arches return a 64bit counter.
As a result of fixing this, removed -Wno-format switch in the test app
which caused the need to fix a lot of printfs.
Haven't built for a pre-armv6 or v6 + thumb machine in a long time and
the effort needed to maintain that is not really worth it. Officially
remove the old support code.
Now you need to include arch/atomic.h to get to the atomic routines.
This simplifies a recusion issue in the way arch/ops.h included
arch_ops. Also just generally makes things cleaner.
Easy to do except for the legacy compile case for i386, in which case we
have to start defining fallthrough atomic routines that the compiler
will call.
At the moment only implement __atomic_fetch_add_4 since its the only one
in use.
Previously, was relying on a regular definition with the arch_ops.h code
overriding it with a static inline. This has been annoying for some
years since it forces the declarations to be in order. Change it to
simple declare an inline wrapper around an arch_ routine that does
whatever it needs to do.
Start using PHDRS and MAXPAGESIZE, remove some extraneous stuff.
Possible we can combine a lot of these linker scripts for various arches
if we're careful.
Implements both SV39 and SV48. No 32bit support yet.
Currently implements basic setup of paging in start.S by mapping a large
chunk of memory into both an identity map and to the bottom of the
kernel address space. Run the kernel out of this physical mapping.
Added basic arch mmu support for querying existing paging structures and
mapping 4K pages. No unmap support as of yet.
System boots with mmu on when running supervisor test on qemu. Untested
on real hardware as of yet.
Add a define that sets the maximum allowed hart number, potentially
higher than the maximum number of allowed cpus.
This lets us more cleanly deal with having a higher HART number than the
logical cpu numbering. Only really works where it's still fairly packed
around 0, but in the case of the Sifive Unleased board it's just offset
by 1 so it's not a huge loss.
Generally clean up RISCV SMP boot code by rearranging things a bit as
well.
Set -fno-builtin to keep the compiler from generating load/stores using
sse outside of floating point code. Not ideal for a lot of reasons but
it's difficult to segregate kernel code and user code such that it only
generates SSE instructions there.
Will probably need to do some work to let certain flags be set per
module, and then have only some of the modules be marked as user vs
kernel.
For one of the riscv embedded targets, the clock ticks at such a slow
rate that the compiler will warn of a div by zero. Add a compile time
hack for this.
Add support for running LK in supervisor mode or machine mode.
- Macro-ify CSR access to use correct CSR # or use SBI call as req'd
- Add support to make SBI calls
- Split CLINT and lk timer abstraction so that RISC-V timer can use SBI
as required.
- Add support for booting other harts as primary since hart0 on U540
does not support S-mode. A map is used to get LK cpu number from
hartid.
Support mp lk start on RISC-V. Several changes throughout were required:
- Add signal in asm start to force secondary harts to wait for bss to be
cleared.
- Use mhartid in arch_curr_cpu_num, PLIC, and CLINT
- Use tp register as thread pointer instead of global variable.
- Support sending IPIs between harts using CLINT
- Add spinlock implementation
Most of changes were moving around where macros were defined, plus the
following:
- Remove requirement for floating point on RV64 to support booting
monitor core on U54 SoC.
- Add support for Debug LEDs on HiFive Unleashed Board
* Adds target tms570-launchpad, for TI TMS570 Launchpad Dev Kit
(https://www.ti.com/store/ti/en/p/product/?p=LAUNCHXL2-TMS57012)
* Adds CPU definitions for Cortex R4F (BE) CPU, implementing
ARMv7-R ISA. Does not yet add definitions for ARMv7 arch entry
functions.
* Board does not yet build - platform.c/uart.c are empty, no GIC
entry points provided.
Tweak the novm allocator to let us more easily add a variable sized
arena at boot.
Also added code to trap secondary cpus and reenable the use of WFI
instruction.
Very little needed to port except to conditionalize some assembly in the
context switch and exception code. Mostly needed to move build system
stuff around and add a new project.
The virt machine is a generic target, much like the arm virt machine.
Intended to be simple to use and a good target to run large systems like
linux on. At the moment simply support booting and simple uart and timer
support.
TL;DR most uses of lib/console.h -> lk/console_cmd.h
Move the part that lets a piece of code somewhere in the system to
define a console command from the actual lib/console api to start an
instance of the console. Move in almost every place the user of the
console command definition to the new header, lk/console_cmd.h which is
always in the include path.
Also remove most uses of testing for WITH_LIB_CONSOLE since you can
almost always just safely define it and then let the linker remove it.
Examples are include/platform.h -> platform/include/platform.h
include/target.h -> target/include/target.h
The old model generally considered these to be Always There includes,
but they're starting to stick out more and more so may as well actually
follow the model that most of the rest of the system follows.
Almost nothing changes here except moving braces to the same line as the
function declaration. Everything else is largely whitespace changes and
a few dangling files with tab indents.
See scripts/codestyle
-added support for bringing up the clocks and setting up the gpio bits
before starting the uart.
-add a proper target init routine
-add scripts to flash board via openocd
-fixed bug in riscv interrupt save state where it wasn't saving mstatus
on irq entry.
-comment out cycle enabling, not implemented on this core
-Add support for x86 legacy mode, designed for 386+ instead of pentium+
-Fixup uart driver to support com2
-Stub out PCI driver properly
-Fixup IDE driver to detect legacy disks
