Commit Graph

677 Commits

Author SHA1 Message Date
Travis Geiselbrecht
c2d77234c3 [arch][riscv] switch to using a boot lottery to dynamically assign cpu number
Turns out that in some cases we can't really rely on a particular boot cpu id
so go ahead and simply dynamically assign cpu numbers by having each cpu
increment an atomic number in the very top of start.S. The first one in gets
the worm.
2020-12-30 00:52:41 -08:00
Travis Geiselbrecht
3194e45807 [arch][riscv][sbi] add probe for new SRST extension 2020-12-09 02:15:29 -08:00
Travis Geiselbrecht
8869020ae2 [arch][riscv] fix bug with gcc 10.2 & binutils 2.35 with section padding
In a two segment binary was previously trying to use MAXPAGESIZE set to 4
to cram the sections in very tight for embedded. This seemed to with this
toolchain cause the linker to get confused and sometimes appear to stuff in
an extra 4 bytes in the output file, thus misaligning the data segment.

It's possible it's still a bug on my side in the linker, but setting
max_page_size to 8 seems to work around it for now. Possible there's some
implicit 64bit aligning slipped in a stage somewhere in binutils thats
causing it to get confused. Either way, 8 byte alignment is no large loss
here.
2020-12-09 01:59:16 -08:00
Travis Geiselbrecht
01f9a97dc1 [arch][openrisc] fix up and get the OpenRISC port working again
Previous to now it had always relied on a custom patched gcc
and a custom sim. In the interim since the initial port went in
some time in 2015 GCC and QEMU have both officially picked up support
for the architecture and the machine that was emulated in the previous
emultor.

Using gcc 10.2 fix up the build and get it basically working. Timers
seem to not be working right but it's probably fairly easy to fix.
2020-10-21 02:34:50 -07:00
vannapurve
945cd5ecdb [ARCH][ARM64] Dump more information during aborts
1) Decode FSC and dump more human readable status
2) Add support of stack unwinding as referred from
arm64 procedure call standard and frame pointer usage.
3) Compiler options for not omitting frame pointer
are enabled to ensure usage of frame pointers even
with higher optimization levels enabled.

Signed-off-by: vannapurve <vannapurve@google.com>
2020-10-13 16:16:15 -07:00
Travis Geiselbrecht
60972b36c1 [arch][arm][cortex-m] select the simplified arch interrupt save/restore for armv6m too
Previously had only selected armv7m for the simplified version.
Forgot that cortex-m0s are armv6m and could use this version.
2020-10-11 03:27:27 -07:00
Michael Bishop
71687b4cbf [arch][arm] fix booting when in HYP mode 2020-10-10 00:58:38 -07:00
Venkatesh Srinivas
c4cdc17865 [platform][tms570-launchpad] Do not try to save d16-d31 on ARMv7-R
All shipping ARMv7-R processors include VFPv3-D16, a subset of VFPv3
with only 16 double-precision registers. The first -R profile CPU
with a complete VFP or NEON implementation is the Cortex-R52,
implementing ARMv8-R.

LK's context switch code had a dynamic check and would only save
d16-d31 if present, but gcc/gas will not assemble code that includes
references to d16-d31 when mcpu=cortex-r4f or other v7-R CPUs.

Ideally we'd key the #if off of __TARGET_FPU_VFPV3_D16, but that
only appears to be defined by the ARM compilers, not gcc. Use
V7-R as the key instead.
2020-10-09 00:58:32 -07:00
Travis Geiselbrecht
7707ab3897 [arch][riscv] specify the target binary format on links, expand exception code
This allows the use of the riscv64-elf toolchain to link riscv32 binaries
and vice versa.

Also add some helpful printfs to the exception code.
2020-07-26 23:41:27 -07:00
Travis Geiselbrecht
f7d8e2300c [warnings] add -Wshadow which helps detect local variables that override globals
Nothing particularly bad showed up but cleaned up a bit of code.
2020-07-25 16:49:25 -07:00
Travis Geiselbrecht
4edb93adde [lib][console] rename some console command types to be prefixed with console_
Some of the structures, notably 'cmd', in the lib console stuff are a
little too generically named and have collided with some other code
so prefix the names a bit more cleanly with console_

The change is largely mechanical, and folks with out of tree code can
easily switch by renaming:
cmd -> console_cmd
cmd_args -> console_cmd_args
cmd_block -> console_cmd_block
console_cmd -> console_cmd_func

Apologies if this breaks you but it should be pretty easy to fix.
2020-07-25 15:59:58 -07:00
Travis Geiselbrecht
5690a8bb58 [arch] make sure the arch rules file sets TOOLCHAIN_PREFIX, make sure riscv picks up the alt selector
ARCH_riscv*_TOOLCHAIN_PREFIX should override TOOLCHAIN_PREFIX like it does on some other arches.
While was at it clean up the rules.mk file a bit.
2020-07-12 13:41:11 -07:00
Travis Geiselbrecht
dac96bea90 [asm] add END_FUNCTION and END_DATA macros and mark up some riscv assembly
Doesn't really do much but at least sets the symbol size properly in a
symbol dump.
2020-07-12 13:41:11 -07:00
Travis Geiselbrecht
4ca59c9237 [arch][riscv] tweak the linker scripts to better place .sdata and .sbss
Refactor the two linker scripts to put .sdata at the end of the data segment
and .sbss at the start of the bss segment to try to maximize the reach of
the global pointer.

Also generally tries to clean up and align the two linker scripts as a new
golden standard for other architectures.
2020-07-11 15:33:14 -07:00
Travis Geiselbrecht
52862d04c7 [arch][riscv] Add a space in some linker script logic
For some reason on older binutils the lack of space around the divide
seems to be a problem.
2020-05-17 13:54:52 -07:00
Travis Geiselbrecht
1ae28c2b5b [arch][x86] big cleanup of the x86.h header
Mostly deduplicating x86-32 and x86-64 code since virtually all of it
can be shared.

Fixed up some cpuid usage which was not properly marking registers as
clobber.
2020-05-16 20:28:17 -07:00
Travis Geiselbrecht
aaafac5903 [arch][arm-m] optimize the arch_interrupt_save routine a bit for cortex-m
From looking at the dissassembly the compiler wasn't doing a good job
with the overly complicated version shared with the larger arm cores.
Simplify it by recognizing that you can save the state directly from
PRIMASK and restore it more simply.
2020-05-16 18:54:00 -07:00
Travis Geiselbrecht
80967e78a6 [arch] tweak arch_cycle_count prototype to return a ulong
This lets some arches return a 64bit counter.

As a result of fixing this, removed -Wno-format switch in the test app
which caused the need to fix a lot of printfs.
2020-05-16 17:55:50 -07:00
Travis Geiselbrecht
6e0762fb53 [arch][arm] remove some old dead code for pre armv6 compiles
Haven't built for a pre-armv6 or v6 + thumb machine in a long time and
the effort needed to maintain that is not really worth it. Officially
remove the old support code.
2020-05-16 15:07:55 -07:00
Travis Geiselbrecht
f371fa246b [arch] move the atomic ops into a separate header
Now you need to include arch/atomic.h to get to the atomic routines.
This simplifies a recusion issue in the way arch/ops.h included
arch_ops. Also just generally makes things cleaner.
2020-05-16 15:05:34 -07:00
Travis Geiselbrecht
556c985b0c [arch][arm64] remove some extraneous copy-pasta in the ops header 2020-05-16 14:40:51 -07:00
Travis Geiselbrecht
f8effeba66 [arch][x86] switch x86 to the builtin atomics
Easy to do except for the legacy compile case for i386, in which case we
have to start defining fallthrough atomic routines that the compiler
will call.

At the moment only implement __atomic_fetch_add_4 since its the only one
in use.
2020-05-16 14:29:21 -07:00
Travis Geiselbrecht
d0f1944038 [arch] define the atomic routines in arch-neutral headers and use builtins
Generally move most arches over to using the builtin atomics except for
the few that still require a little bit of work.
2020-05-16 14:29:21 -07:00
Travis Geiselbrecht
c57b661c93 [kernel][thread] change the way get_current_thread is inlined
Previously, was relying on a regular definition with the arch_ops.h code
overriding it with a static inline. This has been annoying for some
years since it forces the declarations to be in order. Change it to
simple declare an inline wrapper around an arch_ routine that does
whatever it needs to do.
2020-05-16 14:29:21 -07:00
Travis Geiselbrecht
3e66ea6361 [arch][riscv] simplify the exception decoding logic
Use the sign bit on the cause register to separate interrupts from
exceptions.
2020-05-16 14:29:21 -07:00
Travis Geiselbrecht
a5e6261e48 [arch][riscv] optimize the bss fill and data copy in start.S
Use full width load/stores based on the bitness of the build. Previous
linker script changes made sure the start/stop symbols are always
aligned.
2020-05-15 02:06:47 -07:00
Travis Geiselbrecht
225bef5a4b [riscv][linker] general cleanup of the linker scripts
Start using PHDRS and MAXPAGESIZE, remove some extraneous stuff.

Possible we can combine a lot of these linker scripts for various arches
if we're careful.
2020-05-15 02:06:23 -07:00
Travis Geiselbrecht
7c9906a5ff [arch][riscv] Initial implementation of MMU for RISC-V
Implements both SV39 and SV48. No 32bit support yet.

Currently implements basic setup of paging in start.S by mapping a large
chunk of memory into both an identity map and to the bottom of the
kernel address space. Run the kernel out of this physical mapping.

Added basic arch mmu support for querying existing paging structures and
mapping 4K pages. No unmap support as of yet.

System boots with mmu on when running supervisor test on qemu. Untested
on real hardware as of yet.
2020-05-10 17:09:48 -07:00
Travis Geiselbrecht
0b6866830d [arch][arm64][mmu] use slightly more efficient pmm_alloc_page routine
Only used when allocating page size aligned page tables, which is the
common case.
2020-05-10 16:51:58 -07:00
Travis Geiselbrecht
d6bba37cec [arch][riscv] make sure the stack is 16 byte aligned for new threads
This is according to the RISC-V ABI, even in 32bit mode.
2020-05-03 19:34:32 -07:00
Travis Geiselbrecht
5fd7168ab9 [arch][riscv] use a simpler access method for current_thread 2020-05-03 18:50:12 -07:00
Travis Geiselbrecht
6dee5a1303 [arch][riscv] add a per cpu structure and point the scratch register at it
Generally spiff up and clean up the MP code and how the cpu to hart and
vice versa translation is handled.
2020-05-03 17:57:46 -07:00
Travis Geiselbrecht
17037d258d [riscv] add a max HART define to deal with offset hart numbering
Add a define that sets the maximum allowed hart number, potentially
higher than the maximum number of allowed cpus.

This lets us more cleanly deal with having a higher HART number than the
logical cpu numbering. Only really works where it's still fairly packed
around 0, but in the case of the Sifive Unleased board it's just offset
by 1 so it's not a huge loss.

Generally clean up RISCV SMP boot code by rearranging things a bit as
well.
2020-03-28 20:33:04 -07:00
Travis Geiselbrecht
5969063a52 [arch][x86][64] Get the 64bit build working again
Set -fno-builtin to keep the compiler from generating load/stores using
sse outside of floating point code. Not ideal for a lot of reasons but
it's difficult to segregate kernel code and user code such that it only
generates SSE instructions there.

Will probably need to do some work to let certain flags be set per
module, and then have only some of the modules be marked as user vs
kernel.
2020-03-07 18:06:01 -08:00
Travis Geiselbrecht
8fbac4302c [arch][riscv] add proper barriers 2020-01-19 16:58:46 -08:00
Travis Geiselbrecht
96359bd05e [arch][riscv] stub out cache and memory barrier ops
Need to implement the barrier ops, but for the moment they're only used
in virtual machines.
2020-01-19 16:16:59 -08:00
Travis Geiselbrecht
dfcc7c3970 [arch][riscv] move some of the riscv specific headers another level deeper 2020-01-19 15:15:59 -08:00
Travis Geiselbrecht
4d080aaef9 [arch][riscv] fix up the smp reschedule ipi delivery 2020-01-19 14:48:25 -08:00
Travis Geiselbrecht
6dbe2b04a7 [arch][riscv] tweak the SMP start code
-Fix a race in start.S depending on which secondary cpus start first
-Add routine to let a platform/target set the cpu count dynamically
2020-01-19 14:47:07 -08:00
Travis Geiselbrecht
90dc9e50ef [platform][sifive-e] get the hifive1 hardware working again
Had rotted a bit. Had to reimplement a few tweaks.
Also generally #if out a lot of the SMP code when unused on riscv.
2020-01-18 18:39:07 -08:00
Travis Geiselbrecht
36afd4e095 [arch][riscv] code formatting
using ./scripts/codestyle which is an astyle wrapper
2020-01-16 23:17:34 -08:00
Travis Geiselbrecht
ccf46eefba [arch][riscv] add timer hack back
For one of the riscv embedded targets, the clock ticks at such a slow
rate that the compiler will warn of a div by zero. Add a compile time
hack for this.
2020-01-16 23:10:35 -08:00
Elliot Berman
e50d7db612 [arch][riscv] Add support for running in supervisor mode
Add support for running LK in supervisor mode or machine mode.
- Macro-ify CSR access to use correct CSR # or use SBI call as req'd
- Add support to make SBI calls
- Split CLINT and lk timer abstraction so that RISC-V timer can use SBI
  as required.
- Add support for booting other harts as primary since hart0 on U540
  does not support S-mode. A map is used to get LK cpu number from
  hartid.
2020-01-16 23:06:28 -08:00
Elliot Berman
acfe991c7f [arch][riscv] Expose RISC-V mp kernel start
Support mp lk start on RISC-V. Several changes throughout were required:
- Add signal in asm start to force secondary harts to wait for bss to be
  cleared.
- Use mhartid in arch_curr_cpu_num, PLIC, and CLINT
- Use tp register as thread pointer instead of global variable.
- Support sending IPIs between harts using CLINT
- Add spinlock implementation
2020-01-16 23:06:28 -08:00
Elliot Berman
d239adf839 [arch][riscv] Add basic support for SiFive HiFive Unleashed
Most of changes were moving around where macros were defined, plus the
following:
- Remove requirement for floating point on RV64 to support booting
  monitor core on U54 SoC.
- Add support for Debug LEDs on HiFive Unleashed Board
2020-01-16 23:06:28 -08:00
Venkatesh Srinivas
128890f8a8 [platform][tms570-launchpad] Skeleton of port to TI LaunchXL2-TMS57012
* Adds target tms570-launchpad, for TI TMS570 Launchpad Dev Kit
(https://www.ti.com/store/ti/en/p/product/?p=LAUNCHXL2-TMS57012)

* Adds CPU definitions for Cortex R4F (BE) CPU, implementing
  ARMv7-R ISA. Does not yet add definitions for ARMv7 arch entry
  functions.

* Board does not yet build - platform.c/uart.c are empty, no GIC
  entry points provided.
2019-11-18 15:36:28 -08:00
Travis Geiselbrecht
bff17f7e99 [platform][riscv] add code to read the size of memory from the FDT
Tweak the novm allocator to let us more easily add a variable sized
arena at boot.

Also added code to trap secondary cpus and reenable the use of WFI
instruction.
2019-11-02 18:13:02 -07:00
Travis Geiselbrecht
fdc08a8446 [arch][riscv] port to riscv64
Very little needed to port except to conditionalize some assembly in the
context switch and exception code. Mostly needed to move build system
stuff around and add a new project.
2019-11-02 17:21:13 -07:00
Travis Geiselbrecht
ae5200595c [platform][riscv-virt] added support for QEMU's riscv 'virt' machine
The virt machine is a generic target, much like the arm virt machine.
Intended to be simple to use and a good target to run large systems like
linux on. At the moment simply support booting and simple uart and timer
support.
2019-11-02 14:19:36 -07:00
Travis Geiselbrecht
6cb02526b7 [include][console] split lib/console.h into two
TL;DR most uses of lib/console.h -> lk/console_cmd.h

Move the part that lets a piece of code somewhere in the system to
define a console command from the actual lib/console api to start an
instance of the console. Move in almost every place the user of the
console command definition to the new header, lk/console_cmd.h which is
always in the include path.

Also remove most uses of testing for WITH_LIB_CONSOLE since you can
almost always just safely define it and then let the linker remove it.
2019-07-13 16:56:33 -07:00