Commit Graph

82 Commits

Author SHA1 Message Date
Travis Geiselbrecht
bcfad25587 [arch][x86][mmu] update how mmu code accesses physical pages
Move the mmu_initial_mapping from platform into arch/x86. For this
architecture the default mappings are basically hard coded in arch/x86
anyway, so move ownership of this data there, closer to where it's
actually initialized.
Update the 32 and 64bit paging code to properly use the paddr_to_kvaddr
and vice versa routines.
Update to allocate page tables directly from the pmm instead of the heap
(on 32bit code).
2022-11-02 23:48:49 -07:00
Travis Geiselbrecht
0d0568612a [lib][acpi_lite] update to use the VMM to map acpi tables in
The old method assumed that all of the tables were mapped within the
kmap area of the kernel. This basically works on 64bit machines but on a
32bit x86 its entirely likely the ACPI tables are at higher physical
addresses that can be reached, which is currently limited to 1GB.

By using the VM it means it can individually map the headers and each
individual table.
2022-11-02 21:44:15 -07:00
Travis Geiselbrecht
62e2e7dba0 [platform][pc] move the multiboot header into generic space
Share the header with arch/x86 code
Clean up the use of the boot flags
Add code to print the framebuffer information, if present
2022-08-07 23:04:23 -07:00
Travis Geiselbrecht
8643334914 [platform][pc] update the multiboot memory detection code
Parse up to 16 pmm arenas from the multiboot memory data structure. Roll
the 32bit code to properly trim at 1GB as before, but using new logic.
Remove conditional checks on WITH_KERNEL_VM in x86 code, which only
really compiles with the mmu and the vm on.
2022-08-07 16:28:03 -07:00
Travis Geiselbrecht
c429ffcc7a [arch][x86] add more comprehensive feature bit routine
Cache copies of the first few cpuid leaves from each bank at bootup if
present. Add a fast routine to test feature bits out of this array.
2022-07-24 16:59:45 -07:00
Travis Geiselbrecht
fe28bd8a95 [lib][minip] add a mechanism to wait for the stack to be configured
Configured in this case means an ip address assigned and a nic
installed.
2022-03-19 14:46:01 -07:00
Travis Geiselbrecht
f1431b81d0 [bus][pci] Support for dynamically assigning BARs and bridges if needed
In the case of platforms where a bios or firmware has not already
assigned all the resources, do so. Requires the platform supply one or
more ranges of physical address space and IO that can be mapped into
BARs.

Handles iterating through bridges, computing the sizes of all the
peripherals downstream and rolling that up as well.
2022-02-06 19:46:39 -08:00
Travis Geiselbrecht
36e73e0fac [bus][pci] add routines to pass in PCI bus resources prior to starting the pci bus manager
Wire them up on arm and riscv which need them. x86-pc does not, so dont
call it.

Also fix a few miscellaneous bugs, notably PCI not detecting 64bit bars
properly due to an off by one bit error.
2022-02-06 19:46:39 -08:00
Travis Geiselbrecht
2ab1af0bf3 [bus][pci] add a virtual module that references all the pci drivers
Not sure if this is the right way to go forward, but it at least keeps
from having to copy/paste the same module list in a few different
places.
2022-02-06 19:46:39 -08:00
Travis Geiselbrecht
4d276a2406 [platform][pc] add a routine to read the cmos memory 2022-01-09 18:20:14 -08:00
Travis Geiselbrecht
caafb3e2ad [dev][net][e1000] First stab at a working e1000 driver.
-Works against qemu's e1000 and e1000e driver.
-Untested on real hardware yet.
2021-12-27 22:24:31 -08:00
Travis Geiselbrecht
fb1e414a09 [dev][bus][pci] major refactor of the PCI bus driver
-Add a bus manager level, which is an object oriented walk of the pci
busses to build a per device object for later manipulation.
-Add features to enable MSI interrupts.
-Extend generic interrupt api to allow the platform to allocate vectors
for MSI interrupts.
-Rearrange a bit of the pc platform for the platform api changes.
-Add PC platform support for using the local apic to EOI MSI vectors.
-Fix up a few existing PCI drivers for small API changes.
-Add a few stubbed out routines for non PC platforms that use PCI.
2021-12-27 22:24:31 -08:00
Travis Geiselbrecht
a23282cc30 [platform][pc] print some ACPI table information at boot 2021-11-12 21:07:53 -08:00
Travis Geiselbrecht
0c27d8fe45 [bus][pci] first stab at PCI-e ECAM support 2021-11-12 20:44:47 -08:00
Travis Geiselbrecht
ff0f09ae4d [lib][acpi_lite] add definition of MCFG table
MCFG describes the PCIe memory configuration region. Add support for
this table and print the information on boot on PC.
2021-11-11 01:00:18 -08:00
Travis Geiselbrecht
0cf8b5b3c6 [platform][pc] add acpi_lite to the build
Probe ACPI after threads are up and running. Does nothing at the moment
except probe.
2021-11-11 00:16:40 -08:00
Travis Geiselbrecht
a2b41c11d2 [dev][pci] move the pci console commands into the pci bus driver
Remove app/pcitests since it was just the console commands.
2021-11-09 00:19:53 -08:00
Travis Geiselbrecht
445f3e4ee7 [platform/target][warnings] fix -Wmissing-declarations warnings in platform/ and target/
Mostly driver code in various platforms. There are still some warnings
in this part of the tree in lesser-used platforms.
2021-10-21 23:18:09 -07:00
Travis Geiselbrecht
a44bc7863d [dev][bus][pci] move the pci driver out of platform/pc into generic space
No functional change.
2020-03-07 18:17:36 -08:00
Travis Geiselbrecht
3aecdda231 [includes] replace header guards with #pragma once 2019-07-13 15:46:16 -07:00
Travis Geiselbrecht
cba9e47987 [license] replace the longer full MIT license with a shorter one
Used scripts/replacelic. Everything seems to build fine.
2019-07-05 17:22:23 -07:00
Travis Geiselbrecht
d8fa82cb91 [formatting] run everything through codestyle
Almost nothing changes here except moving braces to the same line as the
function declaration. Everything else is largely whitespace changes and
a few dangling files with tab indents.

See scripts/codestyle
2019-06-19 21:02:24 -07:00
Travis Geiselbrecht
1b7a28efb8 [include][lk] fixup lk/ include path move 2019-06-19 19:46:11 -07:00
Travis Geiselbrecht
4c29a608e9 [platform][pc] fix up bios32 PCI support, get pci IDE working again
-Spiff up the device driver starting logic to allow for statically
started devices, instead of always automatic.
2018-12-31 16:47:32 -08:00
Travis Geiselbrecht
1fbb67228d [platform][pc] get working on legacy 386 PC
-Add support for x86 legacy mode, designed for 386+ instead of pentium+
-Fixup uart driver to support com2
-Stub out PCI driver properly
-Fixup IDE driver to detect legacy disks
2018-12-30 21:08:58 -08:00
Travis Geiselbrecht
5dea3e1933 [warnings] fix a few warnings introduced with newer version of gcc
Most of the warnings are new, such as needing to mark fallthroughs on
cases explicitly. A few are based on signed vs unsigned comparisons.

Disable one warning that was annoying about comparing null to arguments
marked nonnull.
2018-03-15 14:10:12 -07:00
Xi Wang
63fa995789 [platform][pc] fix memory map handling in multiboot
The starting address of mmap is off by 4 bytes.

Signed-off-by: Xi Wang <xi.wang@gmail.com>
2017-07-29 21:34:26 -07:00
Xi Wang
9fa0924c88 [platform][pc] fix multiboot info constants
The values of several MB_INFO_* macros are incorrect.

Signed-off-by: Xi Wang <xi.wang@gmail.com>
2017-07-29 21:34:26 -07:00
klemens
d0b90c2d68 [spelling] spelling-fixes. (not external/) 2016-08-25 17:30:34 -07:00
Travis Geiselbrecht
ee672a5471 [arch][x86] flatten x86-64 and x86 into a single tree of code
Major refactor of x86 code into a single arch.
Also bump both 32 and 64 bit to running the kernel at a 'high' address.
2016-02-29 12:42:45 -08:00
Travis Geiselbrecht
d569c090ea [vim] remove vim expandtab comments on most of the files 2016-02-14 12:32:07 -08:00
Travis Geiselbrecht
2eb32a4369 [style] mass reformat all the non external code to 4 space indents
Ran everything through scripts/codestyle.space, which uses astyle
to generally follow K&R style.

Biggest non whitespace change is pulling brackets down on function
declarations, which I'm pretty ambivalent about, but astyle insists
on taking a stance
2016-02-14 12:24:01 -08:00
Zhu, Bing
6216532654 [arch][x86][x64][fpu]fix compile failure when X86_WITH_FPU is not defined.
With this patch, no compile failure issue when either X86_WITH_FPU not defined
or defined as 0(1).

Signed-off-by: Zhu, Bing <bing.zhu@intel.com>
2015-11-25 13:36:04 -08:00
Zhu, Bing
b6647f5bef [arch][x86][fpu]Change naming convention for FPU flag
To align with lk/arm flag naming convention, FPU flag
ENABLE_FPU is changed to X86_WITH_FPU

Signed-off-by: Zhu, Bing <bing.zhu@intel.com>
2015-11-09 22:14:11 +08:00
Travis Geiselbrecht
5030e3e8c8 [platform][pc] mass reformat of pc platform to space indents
used ./scripts/codestyle.space
2015-11-06 19:32:51 -08:00
Travis Geiselbrecht
c6b6a22cdd [platform][pc] change the default heap implementation for PC to dlmalloc 2015-11-06 19:32:51 -08:00
Bing Zhu
60c8eb2e56 [arch][x86_64][mmu] fix virtual addr and physical addr validity check
Canonical address is meaningful only for VIRTUAL address, for physical
address, just check max supported address reported by CPUID capability.
2015-11-05 16:52:03 -08:00
Gabe Black
e092ff3605 [platform][pc] Handle '\r' separately in the graphic console driver.
The code which handled '\n' both went to the next line (new line) and returned
to the left side of the screen (carriage return). It should only do the first,
and carriage return should be handled by '\r'.
2015-10-29 12:30:50 -07:00
Gabe Black
43d37f0cab [platform][pc] Add a carriage return if a newline is encountered in dprintf. 2015-10-29 12:30:50 -07:00
Travis Geiselbrecht
fcaac23cf6 [platform][pc] fix warnings in pc platform 2015-10-27 13:22:34 -07:00
yu-cheng yu
0400a04945 [arch][x86] This is floating point support for intel x86 and x86-64.
Change-Id: Id0b0e2b69c1d27832eb656935e944c04681b324a
2015-10-27 13:04:45 -07:00
Travis Geiselbrecht
3b2d7a268b [make] remove the need for a module to manually add $(LOCAL_DIR)/include to the global include path
Pretty much every module in the system was already doing it, so do it
automatically.
2015-10-19 19:07:16 -07:00
Travis Geiselbrecht
713e138de9 [arch][x86] clean up the way memory size is detected and the vm initialized
Also fix a few warnings in arch/x86
2015-10-11 14:09:55 -07:00
Travis Geiselbrecht
3d096a3e60 [merge] merge pending changes from Intel for x86 and x86-64
Intel repo at https://github.com/srodrig1/lk
2015-10-11 12:27:25 -07:00
Travis Geiselbrecht
8834b12f97 [dev][net][pcnet] break pcnet driver out of pc plaform into its own dir 2015-10-11 12:04:44 -07:00
Sergio Rodriguez
0d635562d7 Adding one shot timer option 2015-09-11 13:24:10 -07:00
Shreyas Nagaraj
57a08b7f65 [arch] [x86] - changes to MMU for x86, x86-64 and x86-PAE
fixing bugs in page table mgmt and overall MMU code clean-up

Signed-off by: Shreyas Nagaraj <shreyas.nagaraj@intel.com>
2015-07-01 00:36:12 -04:00
Sergio Rodriguez
f847e3470f removing redundant hash define 2015-06-11 16:19:09 -07:00
Travis Geiselbrecht
45d56cc2e1 [arch][x86] get x86 building and working again after SMP changes
-Add UP spinlock routines and irq save/restore
-fix platform/pc drivers to use spinlocks instead of critical_section
2015-03-10 16:43:55 -07:00
Sergio Rodriguez
737b76684c [arch][x86-64] Adding Virtual memory support with a 1 to 1 mapping 2014-12-11 19:22:58 -08:00