Not exactly what we want but avoids the lapic code needing the per cpu
structures which aren't set up without SMP support.
Consider leaving the percpu structure in, just only support for cpu 0.
This fixes trying to boot the X86_LEGACY build on a machine with a local
apic.
Doesn't do much but provided the detection path for it and ability to
hold initialized state. The higher level platform code is going to need
to use it directly so will mostly just provide an api for access to it.
Moved ACPI sniffing back to just after the VM is initialized instead of
all the way into platform_init(). This should try to ensure that all
drivers that come up afterwards will have ioapics discovered in case
future development tries to enable and use them, kicking the machine out
of virtual-wire-mode.
I have a bulldozer machine here that curiously starts the APIC IDs for
the cpus at 16 and counts up.
This is a problem since the current code assumes that the boot cpu is 0,
and would try to start itself (apic id 16) later because it thought it
was the first secondary. Fix this by re-reading the APIC id on the boot
cpu and patching the percpu structure a bit into boot. Kinda a hack but
avoids having to detect the APIC, find the type of ID to read, etc.
Also means that practically speaking the system is using the full 32bit
APIC IDs if that feature is present, since now the local apic id is
entirely read from the local apic as it should be (if present).
Fixes#475
A large pile of changes to the PC platform and x86 architecture that
facilitate SMP support. Tested in both 64 and 32bit on qemu and real
hardware all the way back through i486.
- Skip cpus in the MADT table that are not enabled
- Bump count to 16 cpus
- Move the spurious interrupt vector to 0xff since it needs to end in
0xf on <=P6.
- Fix an assert in local apic code when not using x2apic and starting
secondaries.
- Follow the spec a bit closer and wait up till a second for each
secondary core to start.
-Move the local apic driver to arch/x86
-Add routines to send IPIs between cpus
Something is unstable at the moment and the system crashes after a while
with random corruptions when using SMP.
Extend the PIT driver to allow for one shot timers even though it
monotonically runs a 1kHz tick. This allows it to keep time and provide
one shot events, though only at 1ms resolution.
Rearrange some of the cpu initialization code to be runnable on each cpu
as they come up. Complete the 64bit bootstrap mechanism and call into C
code.
Makes it as far as trying to reschedule via an IPI. Need to implement
local apic based IPI mechanism.
On mac qemu, trying to use the physical timer does not seem to work, but
really the virtual timer is what you should be using most of the time,
especially when running under emulation.
Move common logic into a default routine in platform/power that other
platforms can reuse to implement the general default shutdown logic.
Add helper routines to print the cause.
Refactor the platforms that had substantial halt logic to reuse the
default implementation.
Initialize the uart by passing in the base and irq, as well as a flag
specifying if it's the debug uart and should directly put data into the
console buffer (if present).
This was the driver that triggered the whole thing, since GCC 14.1 was
starting to use more fancier addressing modes that was causing QEMU to
bomb out when using KVM.
The accessing method the compiler is emitting for the *REG32 macros on
arm32 and arm64 is occasionally generating load/stores with writeback.
Though this has worked before, it seems to be rejected with whatever
combination of qemu + linux + hardware on this Raspberry Pi 5.
Convert the register accessors to inline asm that uses basic load/store
instructions, which is really the only correct thing to do now and in
the long run. Add a TODO to move this to reg.h and start to revamp how
registers are accessed across LK, but for now keep it just here to fix
things.
Add the fundamental filesystem structure to attach a VirtualIO 9p
device. With the implementation of VirtIO 9p devices (lk/dev/virtio/9p),
we can use those APIs to connect to a shared folder as a LK filesystem.
Signed-off-by: Cody Wong <codycswong@google.com>
Three platforms had basically duplicated logic that just was pulled into
the fdtwalk library. Fix these up to call into those routines instead.
-qemu-virt-arm
-qemu-virt-riscv
-jh7110 (visionfive 2 soc)
A pretty simple mechanism, a list of extensions added to
RISCV_EXTENSION_LIST make variable is expanded to an underscore
delimited string appended to the end of -march=
Pretty simple but it should work for now.
Instead of setting a counter of the number of secondaries to start, have
platform or target code pass in a list of harts to start instead. This
allows for there to be discontinuties in the layout of the cpu harts, or
in the case of some sifive based hardware, hart 0 is otherwise offline.
- Add the v9p support for arm platform.
- Add an option `-f` to set the shared directory on the host machine to
`do-qemuarm`.
- For example, to use the v9p dir sharing, run the script as:
```
# under `lk/` run the follow command will share the current
# directory `lk/` within LK vm as VirtIO 9p device
scripts/do-qemuarm -f .
```
Signed-off-by: Cody Wong <codycswong@google.com>
Use the legacy version of the memory sizing info that just hands the
kernel 2 implicit ranges: 0 ... X and 1MB ... Y.
Not ideal, but when booting on very old machines without BIOS e820 call
implemented it's all you got.
-Reinitialize the uart bit modes
-Ignore framing/break errors on receive. Unclear why they seem to always
be set in the fifo, but seems to be safe to ignore for now
-Make sure platform_pgetc returns the right error code
-Initialize the output ports to all gpios
Clang's assembler rejects expressions containing e.g. (1u << N) in the
assembler. Instead using numeric expressions for per-privilege level
CSRs, we can prepend `m` or `s`. This also lets the compiler assign the
CSR encoding instead of having to hardcode it in the source code.
