Was already added to arm64, but arch/arm hadn't picked up this feature
yet. Uncovered a few places here or there that wasn't marking code as
float/no-float, but this fixes a problem where newer compilers are
starting to sneak in vector code because they can.
Issue #406
If the cpu is always in thumb mode there's really no reason to pass
this switch and it can and does foul up libgcc selection.
Possible it can be removed entirely since the build system doesn't
really support anything prior to armv7 or armv6 where thumb interwork
became implicit. Unclear if it'll cause linking issues to not have it
set, however.
Haven't built for a pre-armv6 or v6 + thumb machine in a long time and
the effort needed to maintain that is not really worth it. Officially
remove the old support code.
* Adds target tms570-launchpad, for TI TMS570 Launchpad Dev Kit
(https://www.ti.com/store/ti/en/p/product/?p=LAUNCHXL2-TMS57012)
* Adds CPU definitions for Cortex R4F (BE) CPU, implementing
ARMv7-R ISA. Does not yet add definitions for ARMv7 arch entry
functions.
* Board does not yet build - platform.c/uart.c are empty, no GIC
entry points provided.
__FPU_PRESENT is set by platform specific cmsis headers
__FPU_USED is set in the cmsis header if __FPU_PRESENT is 1 and the compiler has been
invoked with code to use the fpu.
This picks up the major work of allowing multiple heap implementations
and enable dlmalloc as an alternate heap to the simple existing one
(now called 'miniheap').
Also added a novm page allocator for memory management on systems too small
or missing an mmu to have a vm. Not much more than a simple bitmap allocator
that the heap pulls from. Allows for other heaps and/or users of physical
memory to coexist and span multiple banks of memory.
If a make variable was modified in a way that would cause the linker
script to need to be regenerated on arches that use generated linker
scripts, make sure we get a fresh copy.
Reuse the same generate-then-replace logic that goes into config.h
files.
Add an architecture specific function which spins for a specific
number of CPU cycles. Currently implemented for ARM-M only.
Change-Id: Idbf2a83186cf5ffa239d644dc732fe3d419431c1
Signed-off-by: John Grossman <johngro@google.com>
Set SMP_CPU_CLUSTER_SHIFT to the number of bits needed within
each cluster.
All clusters except the last one, need to have the name number
of cpus to avoid gaps.
Also, add a SMP_CPU_ID_BITS variable and limit this to 8 bits
on the bcm2835 platform instead of ignoring cluster ids by default
on arm.
Change-Id: I1d0be1d9c99d5b85368ce71623e6e7d14fefd604
This implementation handles ARCH_MMU_FLAG_NS attribute only.
Enable pick spot support if support for non-secure memory
is required (WITH_NS_MAPPING make variable is set to true).
Change-Id: I8f575f36ba729dc148c6320a4e0bbb4c6eec14a4
-add hooks for weirdo bcm2836 interrupt controller
-remove the relaxed thread and mpidr register accessors (may be able to relax them again)
-deal with (or not) cpus with non zero cluster ids
Add kernel/vm code to handle memory management in large page-aligned
regions of virtual space. This is composed via a pmm (physical
memory manager) and vmm (virtual memory manager) and the architecturally
specific code to manage the mmu.
Add ARMv7 paging code.
