Extend the block i/o system to allow registered devices to advertise
an erase geometry. Devices which do not need to be explicitly erased
may skip this. Extent the Zynq spiflash code to publish the erase
geometry as read from the flash device.
Signed-off-by: John Grossman <johngro@google.com>
Change-Id: I42e16fbe9a0fcf8334c317f16dea1c551c203eb2
Instead of conditionalizing arch code booting secondaries, only conditionalize
waiting for each of them to come up.
This should be semi-temporary, as the need to wait will go away once arm
switches entirely to the trampoline page table strategy.
Change-Id: Idbdb9720bfac58adf514b7fa137e59aee413f4df
On some platforms, the secondary cpus have been booted and trapped by the arch/arm code
and need to be brought up lockstep to make sure the temporary page mappings are
still in place as they are booted. For these platforms, set
ARM_ARCH_BOOTS_SECONDARIES=1 to have arch_init() try to release and start the cpus.
For other platforms, after arch_init() they can simply arrange for the secondary cpus
to start themselves.
Change-Id: I7619ac66d84bd26060ddd949ae6641c1ef6e2b1d
-have the zynq nak autobooting if the BOOT_MODE pins were set to
JTAG mode.
-Clean up some of the timeout logic a bit.
Change-Id: I4ace6354de89f2e88aa270e5ebc1bf01ebe3b046
-use lib/watchdog to manage the hardware watchdog driver
-set the default timeout to 1 second, pet at 500ms intervals
Change-Id: I04d23313083e4715791e197d4a50f319df9916aa
+ When setting GPIOs, the MASK_DATA registers are used. Code was
properly computing which register to use based on register index
(either LSW or MSW), but was improperly computing the mask/value to
set when the GPIO to be manipulated existed in the upper 16 bits
(the shift needed to be offset by 16 bits and was not).
+ Do not manipulate things like the IO driver type, drive speed, and
so on when enabling/disabling the pullup in the SLCR registers.
Previously, whenever a GPIO was being configured, the SLCR register
was being set to be 1.8v LVCMOS, and having the DISABLE RCV bit set.
Things like the IO type have been set by the platform and should not
be manipulated by the GPIO driver. Now, the GPIO code leaves those
bits the way they were configured, and changes only the PULLUP bit
as well as the 4 levels mux bits (arguably, it should not even
change the mux bits; it is the platform's job to properly mux the
pins).
+ Address an issue with the subtle (undocumented) difference between
the DIRM and the OEN bits when configuring for input vs. output.
Please read the extensive comment in the code for details.
Change-Id: I160069eeef92b1cf0763274ccb64c5d14744f563
Signed-off-by: John Grossman <johngro@google.com>
Fix an issue with the GPIO code where it was dividing by 31 instead of
32 when attempting to map GPIO numbers to bank IDs.
Change-Id: I986eac1f9dce119445d1611666b61a7b2635ca5b
Signed-off-by: John Grossman <johngro@google.com>
-handle flushing tx/rx buffers
-tweak tx logic to handle multiple tx descriptors per interrupt
-fix subtle race with tx dma engine as descriptors are filled
- GEM now supports asynchronous scatter-gather queuing and properly handling
pktbuf ownership
- General stack cleanups in Minip
- pktbufs now grab buffers from the user, or from a preallocated pool
-statically configure more clk registers at boot
-configure the same number of MIO regsters for 225 vs 400 pin packages
Change-Id: Ib8aab1546ce743d1a58343d492af7626c8b5ce7e
