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lby/lk

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Commit Graph

Author	SHA1	Message	Date
Travis Geiselbrecht	6ea6256d89	[platform][sifive] add switch to scripts/do-riscvqemu to run sifive unleashed Also fix up some broken bits on the previously unused qemu-sifive-u target.	2020-12-30 01:40:05 -08:00
Elliot Berman	e50d7db612	[arch][riscv] Add support for running in supervisor mode Add support for running LK in supervisor mode or machine mode. - Macro-ify CSR access to use correct CSR # or use SBI call as req'd - Add support to make SBI calls - Split CLINT and lk timer abstraction so that RISC-V timer can use SBI as required. - Add support for booting other harts as primary since hart0 on U540 does not support S-mode. A map is used to get LK cpu number from hartid.	2020-01-16 23:06:28 -08:00
Elliot Berman	e137d70ccd	[target][riscv] Add support for qemu-sifive-u virt machine A copy/paste from sifive-unleashed but without PWM/LED.	2020-01-16 23:06:28 -08:00

Author

SHA1

Message

Date

Travis Geiselbrecht

6ea6256d89

[platform][sifive] add switch to scripts/do-riscvqemu to run sifive unleashed

Also fix up some broken bits on the previously unused qemu-sifive-u target.

2020-12-30 01:40:05 -08:00

Elliot Berman

e50d7db612

[arch][riscv] Add support for running in supervisor mode

Add support for running LK in supervisor mode or machine mode.
- Macro-ify CSR access to use correct CSR # or use SBI call as req'd
- Add support to make SBI calls
- Split CLINT and lk timer abstraction so that RISC-V timer can use SBI
  as required.
- Add support for booting other harts as primary since hart0 on U540
  does not support S-mode. A map is used to get LK cpu number from
  hartid.

2020-01-16 23:06:28 -08:00

Elliot Berman

e137d70ccd

[target][riscv] Add support for qemu-sifive-u virt machine

A copy/paste from sifive-unleashed but without PWM/LED.

2020-01-16 23:06:28 -08:00

3 Commits