Some routines inside the sensor bus code in dartuino need floating
point, so put those in MODULE_FLOAT_SRCS.
Also mark app/accellerometer as needing float.
Port to the really neat 68010 based board at https://rosco-m68k.com/
Port Features:
-10Mhz 68010
-1MB ram
-Dual UART + timer implemented as a 68c681 chip
-timer running at 1Khz, UART A for console
-interrupt driven RX support
Some amount of extending of the 68k exceptinon code was needed to
support the autovectored irqs that the 68681 uart uses. Added build
system support for 68010.
Uses the QEMU virt machine for 68k defined in qemu 6.0+.
Basic support that boots, prints to the console, takes input from
console, and context switches.
TODO: interrupt support, timer support.
Uses the target/debugconfig.h file pattern laid down before,
which is a bit long in the tooth but for the moment still helps
us separate target from platform.
- sys/cdefs is wanted for __CONCAT()
- version.h and config_autogen.h are generated by the pico sdk
- config_autogen expects to include board file
- instead define PICO_xyz in target rules.mk
- just a skeleton to get us started
- cpu feature config and irq names / vectab2 setup done
- pulled in the second stage for pico as a blob for now
- seems to be hard faulting out of systick setup in platform_init()
Since the i2c driver is optional (not required for platform) the
i2c_init should be done during target initialization. The flags
used to include the i2c driver should be in either target or project
files so it makes sense that the i2c_init should also be called from
target files.
When the nrf52xxx platform was changed to use the Nordic nrfx
libraries the pca10040 target was broken due to differences in
how the platform handled initialization.
Using Nordic's nrfx driver for the clock control peripheral since
it address a handful of errata and abstracts some differences
in the nrf52 family of parts.
Platform gpio driver now uses the nrfx library for gpio manipulation.
This allows utilization of second gpio bank present on some parts
and handling of errata.
Use twim(i2c) driver from nrfx library. See comments and patterns in
target/nrf-pca10056 for info on how to properly utilize driver as it
requires some GLOBAL_DEFINES and gpio defines.
Some of the structures, notably 'cmd', in the lib console stuff are a
little too generically named and have collided with some other code
so prefix the names a bit more cleanly with console_
The change is largely mechanical, and folks with out of tree code can
easily switch by renaming:
cmd -> console_cmd
cmd_args -> console_cmd_args
cmd_block -> console_cmd_block
console_cmd -> console_cmd_func
Apologies if this breaks you but it should be pretty easy to fix.
No need to malloc this memory if it's always going to be initialized
anyway. Add history disabling switch to a few targets to make sure both
builds are tested.
Only tested with SBI and supervisor mode, but that's all I have now.
Add checked in copies of the device tree needed for a uboot uimage
needed to start it.
Add support for running LK in supervisor mode or machine mode.
- Macro-ify CSR access to use correct CSR # or use SBI call as req'd
- Add support to make SBI calls
- Split CLINT and lk timer abstraction so that RISC-V timer can use SBI
as required.
- Add support for booting other harts as primary since hart0 on U540
does not support S-mode. A map is used to get LK cpu number from
hartid.
Support mp lk start on RISC-V. Several changes throughout were required:
- Add signal in asm start to force secondary harts to wait for bss to be
cleared.
- Use mhartid in arch_curr_cpu_num, PLIC, and CLINT
- Use tp register as thread pointer instead of global variable.
- Support sending IPIs between harts using CLINT
- Add spinlock implementation
Most of changes were moving around where macros were defined, plus the
following:
- Remove requirement for floating point on RV64 to support booting
monitor core on U54 SoC.
- Add support for Debug LEDs on HiFive Unleashed Board
* Adds target tms570-launchpad, for TI TMS570 Launchpad Dev Kit
(https://www.ti.com/store/ti/en/p/product/?p=LAUNCHXL2-TMS57012)
* Adds CPU definitions for Cortex R4F (BE) CPU, implementing
ARMv7-R ISA. Does not yet add definitions for ARMv7 arch entry
functions.
* Board does not yet build - platform.c/uart.c are empty, no GIC
entry points provided.
The virt machine is a generic target, much like the arm virt machine.
Intended to be simple to use and a good target to run large systems like
linux on. At the moment simply support booting and simple uart and timer
support.
TL;DR most uses of lib/console.h -> lk/console_cmd.h
Move the part that lets a piece of code somewhere in the system to
define a console command from the actual lib/console api to start an
instance of the console. Move in almost every place the user of the
console command definition to the new header, lk/console_cmd.h which is
always in the include path.
Also remove most uses of testing for WITH_LIB_CONSOLE since you can
almost always just safely define it and then let the linker remove it.
Examples are include/platform.h -> platform/include/platform.h
include/target.h -> target/include/target.h
The old model generally considered these to be Always There includes,
but they're starting to stick out more and more so may as well actually
follow the model that most of the rest of the system follows.
Almost nothing changes here except moving braces to the same line as the
function declaration. Everything else is largely whitespace changes and
a few dangling files with tab indents.
See scripts/codestyle
-added support for bringing up the clocks and setting up the gpio bits
before starting the uart.
-add a proper target init routine
-add scripts to flash board via openocd
-fixed bug in riscv interrupt save state where it wasn't saving mstatus
on irq entry.
-comment out cycle enabling, not implemented on this core
-Add support for x86 legacy mode, designed for 386+ instead of pentium+
-Fixup uart driver to support com2
-Stub out PCI driver properly
-Fixup IDE driver to detect legacy disks
Currently targets qemu's sifive_e machine, which is a split flash/ram
machine, much like the Sifive HiFive1. Untested as of yet on a real
HiFive1.
Basic support including interrupts and architectural timers in place.
