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52 Commits

Author SHA1 Message Date
Travis Geiselbrecht
6ad3643165 [lib][minip] add an arg to the ethernet transmit callback 
Already had the registration hook for it, but was never used.
 2022-03-19 15:06:57 -07:00
Travis Geiselbrecht
3aecdda231 [includes] replace header guards with #pragma once 2019-07-13 15:46:16 -07:00
Travis Geiselbrecht
cba9e47987 [license] replace the longer full MIT license with a shorter one 
Used scripts/replacelic. Everything seems to build fine.
 2019-07-05 17:22:23 -07:00
Travis Geiselbrecht
1b7a28efb8 [include][lk] fixup lk/ include path move 2019-06-19 19:46:11 -07:00
Travis Geiselbrecht
96ba54f187 [merge] merge back from smp branch 2015-05-28 12:52:41 -07:00
Travis Geiselbrecht
f13ebc12f5 [platform][zynq] add code to read the BOOT_MODE pins sampled at power on 
Change-Id: I2745b4aa5d63f1f8d6630836fec88ae0577feb7d
 2015-05-20 23:31:39 -07:00
Travis Geiselbrecht
307628f29b [platform][zynq] add watchdog driver 
-use lib/watchdog to manage the hardware watchdog driver
-set the default timeout to 1 second, pet at 500ms intervals

Change-Id: I04d23313083e4715791e197d4a50f319df9916aa
 2015-05-20 23:31:39 -07:00
John Grossman
c2b645ef8a [zynq][gpio] Fix a collection of bugs with the GPIO driver. 
+ When setting GPIOs, the MASK_DATA registers are used.  Code was
  properly computing which register to use based on register index
  (either LSW or MSW), but was improperly computing the mask/value to
  set when the GPIO to be manipulated existed in the upper 16 bits
  (the shift needed to be offset by 16 bits and was not).
+ Do not manipulate things like the IO driver type, drive speed, and
  so on when enabling/disabling the pullup in the SLCR registers.
  Previously, whenever a GPIO was being configured, the SLCR register
  was being set to be 1.8v LVCMOS, and having the DISABLE RCV bit set.
  Things like the IO type have been set by the platform and should not
  be manipulated by the GPIO driver.  Now, the GPIO code leaves those
  bits the way they were configured, and changes only the PULLUP bit
  as well as the 4 levels mux bits (arguably, it should not even
  change the mux bits; it is the platform's job to properly mux the
  pins).
+ Address an issue with the subtle (undocumented) difference between
  the DIRM and the OEN bits when configuring for input vs. output.
  Please read the extensive comment in the code for details.

Change-Id: I160069eeef92b1cf0763274ccb64c5d14744f563
Signed-off-by: John Grossman <johngro@google.com>
 2015-05-19 10:21:33 -07:00
Arve Hjønnevåg
2c9c5959e7 Merge branch 'master' of https://github.com/travisg/lk into smp 
Change-Id: Iecb11d57b6f089234c0826932bdb229588939750
 2015-05-18 16:49:37 -07:00
John Grossman
43d86bfdb0 [zynq][fpga] Add a function to check the FPGA config status. 
Add a small function which checks to see if the FPGA has been
successfully configured yet.

Change-Id: If7c8f4f006b54958cf3052bb5962c964668cd5a9
 2015-04-24 15:53:55 -07:00
Christopher Anderson
4a038ceef6 [zynq] Add support for GPIO interrupts 2015-04-23 13:30:39 -07:00
Christopher Anderson
d352ac1d2b [gem][minip][pktbuf] Improvements for TX scatter gather functionality 
- GEM now supports asynchronous scatter-gather queuing and properly handling
  pktbuf ownership
- General stack cleanups in Minip
- pktbufs now grab buffers from the user, or from a preallocated pool
 2015-04-23 13:30:39 -07:00
Christopher Anderson
165a69ebf0 [zynq] gpio driver cleanup and plumbing for later int work 2015-04-03 16:49:46 -07:00
Christopher Anderson
ffbb7b8fd3 [zynq] Add MIO_DEFAULT and correctly ignore MIO configuration based on that rather than 0 2015-04-02 11:03:55 -07:00
Travis Geiselbrecht
80fbfef0e1 [merge] merge branch 'master' into smp 
Conflicts:
	kernel/vm/pmm.c
	platform/zynq/debug.c
	platform/zynq/platform.c
 2015-03-31 15:35:13 -07:00
Travis Geiselbrecht
8c1f3b0809 [platform][zynq] trap the second cpu in lk's image to reclaim the last 64k of sram 
Change-Id: I7eb6787f967f037670bddbe0eeaa4fb384e04d83
 2015-03-19 20:50:11 -07:00
Travis Geiselbrecht
52c18ef50a [platform][zynq] boottime configuration updates 
-statically configure more clk registers at boot
-configure the same number of MIO regsters for 225 vs 400 pin packages

Change-Id: Ib8aab1546ce743d1a58343d492af7626c8b5ce7e
 2015-03-18 19:26:46 -07:00
Travis Geiselbrecht
99c00354eb [platform] convert platform code for alterasoc, vexpress-a9, and zynq to SMP 2015-03-10 16:43:55 -07:00
Travis Geiselbrecht
a173db1b31 [platform][zynq] add timeout to fpga programming code, only dma 4 byte words (/4) 2014-12-11 20:01:11 -08:00
Travis Geiselbrecht
68f935e613 [platform][zynq] add support for putting the qspi peripheral in linear mode 2014-12-11 19:25:29 -08:00
Chris Anderson
5ed4eca1ba [zynq] Add slcr commands and pull out DDR config 2014-11-21 10:37:00 -08:00
Travis Geiselbrecht
a88d310855 [platform][zynq] detect flash in single spi mode and add command to set qspi mode 
Change-Id: I3d0ea403c79f9b7a8c34c9f871e97bd728b46d7f
 2014-10-13 19:08:22 -07:00
Chris Anderson
e28aeab1ec [zynq][gem] Add ETH1 support 2014-10-10 13:51:31 -07:00
Chris Anderson
3e6334670f [zynq][gem] Move MIO cfg in the gem driver to the target cfg 2014-10-10 13:39:09 -07:00
Chris Anderson
bd20280aa2 [zynq] Fix bug forcing 32bit ddr width when coming out of reset 2014-10-10 13:10:43 -07:00
Chris Anderson
27d679facd [zynq] Add uzed target support 2014-08-27 11:48:18 -07:00
Chris Anderson
e060c035d1 [zynq] Remove generated init for Zybo, add platform init routines 2014-08-27 11:48:18 -07:00
Travis Geiselbrecht
4b91d96f6c [platform][zynq] on DRAM base builds, make sure the sram arena is sized properly 2014-08-15 13:37:21 -07:00
Travis Geiselbrecht
d0abccf707 [platform][zynq] Add F2P IRQ definitions. 
Add the IRQ IDs for the Fabric-2-Processor peripheral IRQs.

Change-Id: I8c9b76c850e15216e410cd8ccad68b23f585cd72
 2014-08-12 16:26:42 -07:00
Travis Geiselbrecht
6c67513c58 [platform][zynq] add hook to disable the gem and hard reset it when initializing 2014-08-12 16:07:50 -07:00
Travis Geiselbrecht
bf222fad5a [platform][zynq] make sure SLCR structure is volatile 2014-08-06 16:00:19 -07:00
Chris Anderson
98a09511e9 [zynq] Convert clk/mio jam table to readable code 
Also re-added the generated pll table for documentation purposes
 2014-08-04 15:54:25 -07:00
Chris Anderson
2b4c03e80e [zynq] Convert the Zynq PLL init jam table into readable code 
End goal will be to convert all the functions and remove ps7 entirely.
 2014-07-31 15:37:03 -07:00
Chris Anderson
4a3ac17349 [gem]/[minip] mac and console changes 
+ Add gem_set_macaddr
+ Disable promiscuous mode
+ Change flood command to raw
+ Change gem's console command from 'g' to 'gem'
+ Add status commands for both minip and gem
 2014-07-31 01:24:40 -07:00
Chris Anderson
c0385aecbe [zynq] Move SLCR access to a struct layout, update clock interface 2014-07-31 00:49:34 -07:00
Chris Anderson
0dda31bddc [platform][zynq] GEM ethernet controller 2014-07-24 17:53:37 -07:00
Chris Anderson
179c2ddd58 [platform][zynq] additional IRQs 2014-07-24 17:53:37 -07:00
Chris Anderson
455bd4e01a [platform][zynq] some slcr register definitions 2014-07-24 17:53:37 -07:00
Travis Geiselbrecht
503f30f685 Merge remote-tracking branch 'github/vm' 
Conflicts:
	platform/vexpress-a9/include/platform/vexpress-a9.h
	platform/zynq/rules.mk
 2014-07-24 01:29:43 -07:00
Travis Geiselbrecht
bcebb0861a [platform][zynq] refactor qspi into two layers 2014-07-15 20:09:08 -07:00
Travis Geiselbrecht
184cac4a0f [platform] add zybo and vexpress-a9 support for the VM 2014-07-11 18:11:59 -07:00
Travis Geiselbrecht
20ef00873a [platform][zynq] enable PL310 L2 cache controller 2014-06-03 21:17:52 -07:00
Travis Geiselbrecht
caaa527172 [platform][zynq] update clock setting api, print boot reason 2014-05-30 17:02:49 -07:00
Travis Geiselbrecht
3e4797c960 [platform][zynq] update clock routines to lock/unlock 2014-05-29 18:51:00 -07:00
Travis Geiselbrecht
bdb5addd5b [platform][zynq] initial implementation of some clock routines 
-Mostly introspection at this point
-Move target specific jam table to early platform init
 2014-05-29 18:24:55 -07:00
Brian Swetland
40fd2b00f9 [platform][zynq] initial fpga control routines 
- zynq_program_fpga(physaddr,len) -- load bitstream
- zynq_reset_fpga() -- reset fpga
 2014-05-26 22:10:41 -07:00
Travis Geiselbrecht
036647ec1d [platform] move alterasoc and zynq timer to the shared generic cortex a9 driver 2014-05-11 00:45:58 -07:00
Travis Geiselbrecht
70581abc91 [platform][zynq] map all of dram as fully cached 2014-05-02 22:30:02 -07:00
Travis Geiselbrecht
a1ce3518bc [platform][zynq] switch to the GIC driver for interrupt controller business 2014-05-01 19:06:50 -07:00
Travis Geiselbrecht
3a463d272d [platform][zynq] interrupt driven uart rx 2014-04-21 01:19:22 -07:00