20 Commits

Author SHA1 Message Date
Travis Geiselbrecht
e4d65228b5 [mp] restructure the sequence of how cpus are brought up
- Move a bit of the shared logic of secondary bootstrapping into a new
  function, lk_secondary_cpu_entry_early() which sets the current cpu
  pointer before calling the first half of the secondary LK_INIT
  routines.
- Create the per cpu idle threads on the main cpu instead of the
  secondary as they come up.
- Tweak all of the SMP capable architectures to use this new path.
- Move the top level mp routines into a separate file top/mp.c
- A bit more correctly ifdef out more SMP code.
2025-10-12 19:47:33 -07:00
Travis Geiselbrecht
e47183725d [arch][arm64] move secondary cpu entry point to separate function
- Make the secondary entry point be logically separate function, though
  declared in the same file.
- Add a trick where the kernel base + 4 is the secondary entry point.
  Not really useful except makes it easy to compute the offset
  elsewhere.
- Changed the entry point to arm64_reset and move _start to the linker
  script, which is what most other arches do.
- While was in the linker script, make sure the text segment is aligned
  on MAXPAGESIZE, though doesn't make any real difference currently.
- Generally clean up the assembly in start.S with newer macros from
  Fuchsia, and avoid using ldr X, =value as much as possible.
- Fix and make sure arm64 can build and run with WITH_SMP set to false.
  Add a new no-smp project to test this.

Note this will likely break systems where all of the cpus enter the
kernel simultaneously, which we can fix if that becomes an issue.
Secondary code now completely assumes the cpu number is passed in x0.
This can be emulated with platform specific trampoline code if it needs
to that then just directs into the the secondary entry point, instead of
trying to make the arch code have to deal with all cases.
2025-10-12 19:47:33 -07:00
Travis Geiselbrecht
91128ad729 [arch][arm64] clean up how secondary cpus are initialized and tracked
- Add a percpu structure for each cpu, akin to x86-64 and riscv. Pointed
  to by x18, which is now reserved for this in the kernel. Tweaked
  exception and context switch routines to leave x18 alone.
- Remove the cpu-trapping spinlock logic that is unused in mainline,
  probably. (Can add a new version of it back if it's necessary).
- Switch fdtwalk helper to using the newer, cleaner way of initializing
  secondaries using the PSCI CPU_ON argument that should be pretty
  standard on modern implementations. (Possibly an issue with old
  firmware).
- Remove the notion of computing the cpu ID from the Affinity levels,
  which doesn't really work properly on modern ARM CPUs which more or
  less abandoned the logical meaning of AFFn.
2025-10-12 19:47:33 -07:00
Travis Geiselbrecht
1684855b9a [dev][psci] clean up the psci driver a bit, add arg to cpu_on
- General cleanup of the driver a bit
- Aadd a boot time message that prints the version
- Add the argument field to CPU_ON
- Pass the cpu number through from fdtwalk library
2025-10-12 19:47:33 -07:00
Travis Geiselbrecht
664bb17afa [ubsan] fix some bugs and warnings discovered by ubsan
- X86 cpuid feature list dump was using the wrong array and walking off
  the end of one.
- GICv2 code had a left shift by up to 31 of an integer. Needs to be
  unsigned.
- PLIC same as GIC code.
- fdtwalker code should be using a bytewise accessor based helper
  function for reading large integers out of an unaliged FDT.
- PCI BIOS32 search code could do a 32bit unaligned read of a string,
  switch to using memcmp.
2025-10-05 15:35:31 -07:00
Travis Geiselbrecht
bd423cad4d [lib][fdtwalk] skip scanning pci busses marked 'disabled' 2024-06-19 16:18:28 -07:00
Travis Geiselbrecht
e3a5f9c363 [lib][fdtwalk] fix some unfound bugs in the riscv isa string detection 2024-06-17 00:45:20 -07:00
Travis Geiselbrecht
566b25d1ec [arch][riscv] read the riscv feature string out of device tree
Also added initial implementation of a way to query run time features of
the cpu.
2024-06-01 17:21:01 -07:00
Travis Geiselbrecht
ec4da9673b [platform][qemu-riscv32] trim usable memory to 1GB on qemu-riscv32 2024-05-16 20:52:45 -07:00
Travis Geiselbrecht
2f98fbf772 [pci][fdt] do not attempt to configure PCI with 64bit bars on a 32bit system
Especially in the case where the 32bit system doesn't have an MMU, avoid
using any high addresses for BARs.
2024-05-09 22:18:19 -07:00
Travis Geiselbrecht
4a97f932fd [lib][fdtwalk] restructure the fdtwalker helper routines
Instead of one large routine that takes a list of optional callbacks,
build some helper routines that do the work that a few platforms have
implemented on their own to share some code between them.

Future enhancements: move some of the helpers out of this library into
the library that implements the thing it's helping with (ie, PCI
bringup, bootstrapping arch specific cores). For now just leave them in
helper.cc which is conditionally compiled.
2024-04-16 23:11:59 -07:00
Travis Geiselbrecht
05540c992a [lib][fdtwalk] trivially convert to C++ 2024-04-16 23:01:31 -07:00
Travis Geiselbrecht
6b7d0ab627 [lib][fdtwalk] add code to skip a cpu if disabled
Some RISC-V cpus come up disabled, skip enumerating them.
2023-10-15 14:41:30 -07:00
Travis Geiselbrecht
91d0a5f7d1 [lib][fdtwalk] add routine to find and parse /reserved-memory node
Add logic to the riscv virt platform to properly mark off memory
claimed by OpenSBI.
2022-12-17 17:12:35 -08:00
Pedro Falcato
a9a631152f [fdtwalk] Fix a bug in #address-cells parsing
Fixes issue #314
2022-02-13 14:00:22 -08:00
Travis Geiselbrecht
06ab680159 [lib][fdtwalk] add support to return the io/mmio pci aperture as well
FDT encodes the range of available mmio and io ports that the PCI bus
can use to map bars. Return this information out of the FDT walker
helper routines to feed into the PCI bus manager in the future.
2022-02-06 19:46:39 -08:00
Travis Geiselbrecht
c9eae714db [platform][qemu-virt-riscv] pick the PCIE ecam out of FDT and initialize PCI bus 2021-11-12 21:23:09 -08:00
Travis Geiselbrecht
b01f7083eb [lib][fdtwalk] add a callback hook to pass back pci-express information
At the moment only picks out the ECAM aperture and start/end bus
information, but enough to bootstrap the pci bus.
2021-11-12 21:05:40 -08:00
Travis Geiselbrecht
811566f03d [lib][fdtwalk] spiff up the fdt walker to read #address-cells and #size-cells
Will now start to handle properly sized cells for future parsing
efforts.
2020-05-03 14:47:22 -07:00
Travis Geiselbrecht
f1dcdfd7a8 [lib][fdtwalk] move some of the duplicate code to parse flattened device trees into a shared lib
Uses a callback structure that various platforms can use to automate
walking through the trees for common nodes.
2020-04-25 18:37:57 -07:00