27 Commits

Author SHA1 Message Date
Travis Geiselbrecht
664bb17afa [ubsan] fix some bugs and warnings discovered by ubsan
- X86 cpuid feature list dump was using the wrong array and walking off
  the end of one.
- GICv2 code had a left shift by up to 31 of an integer. Needs to be
  unsigned.
- PLIC same as GIC code.
- fdtwalker code should be using a bytewise accessor based helper
  function for reading large integers out of an unaliged FDT.
- PCI BIOS32 search code could do a 32bit unaligned read of a string,
  switch to using memcmp.
2025-10-05 15:35:31 -07:00
Travis Geiselbrecht
c9d2f80e43 [dev][interrupt][gicv2] test that this is a GICv2
Add some boot time informational message and read the maximum number of
interrupts supported by this hardware.
2025-10-05 13:57:21 -07:00
Travis Geiselbrecht
ea425e5473 [dev][gicv2] switch all of the register accessors to mmio_*
This fixes a bug when trying to start on qemu + kvm on an arm host.

A few minor fixes as suggested by clang tidy.
2024-06-04 20:28:03 -07:00
Travis Geiselbrecht
f1431b81d0 [bus][pci] Support for dynamically assigning BARs and bridges if needed
In the case of platforms where a bios or firmware has not already
assigned all the resources, do so. Requires the platform supply one or
more ranges of physical address space and IO that can be mapped into
BARs.

Handles iterating through bridges, computing the sizes of all the
peripherals downstream and rolling that up as well.
2022-02-06 19:46:39 -08:00
Travis Geiselbrecht
91d5c67fc2 [platform][qemu-virt] make sure the PCI bus builds properly
Implement stubbed out versions of the msi allocation routines.

Add a stubbed out routine to allocate MSI vectors.
2022-02-06 19:46:05 -08:00
Travis Geiselbrecht
fcb65c9a88 [dev/lib][warnings] fix -Wmissing-declarations warnings in dev/ and lib/ 2021-10-21 23:16:20 -07:00
Travis Geiselbrecht
cba9e47987 [license] replace the longer full MIT license with a shorter one
Used scripts/replacelic. Everything seems to build fine.
2019-07-05 17:22:23 -07:00
Travis Geiselbrecht
d8fa82cb91 [formatting] run everything through codestyle
Almost nothing changes here except moving braces to the same line as the
function declaration. Everything else is largely whitespace changes and
a few dangling files with tab indents.

See scripts/codestyle
2019-06-19 21:02:24 -07:00
Travis Geiselbrecht
1b7a28efb8 [include][lk] fixup lk/ include path move 2019-06-19 19:46:11 -07:00
Payam
6e05388579 [vim2] Initial support for Khadas VIM2 boards 2018-03-16 15:05:10 -07:00
Travis Geiselbrecht
d569c090ea [vim] remove vim expandtab comments on most of the files 2016-02-14 12:32:07 -08:00
Travis Geiselbrecht
2eb32a4369 [style] mass reformat all the non external code to 4 space indents
Ran everything through scripts/codestyle.space, which uses astyle
to generally follow K&R style.

Biggest non whitespace change is pulling brackets down on function
declarations, which I'm pretty ambivalent about, but astyle insists
on taking a stance
2016-02-14 12:24:01 -08:00
Travis Geiselbrecht
3b2d7a268b [make] remove the need for a module to manually add $(LOCAL_DIR)/include to the global include path
Pretty much every module in the system was already doing it, so do it
automatically.
2015-10-19 19:07:16 -07:00
Travis Geiselbrecht
caec70a21b [dev][arm_gic] fix warning in arm64 by adding arm/arm64 specific iframe code
It's all in service of a LTRACEF, but it's one I use commonly enough to debug
stuff that it's probably worth it. No actual overhead, except what's already
in the first level handlers.
2015-09-20 14:05:31 -07:00
Arve Hjønnevåg
c027dbd0d4 [dev][interrupt][arm_gic] Fix fiq code to get cpu number from arch_curr_cpu_num
Fixes fiq support on multicluster systems.

Change-Id: If19a78b580eec79b7194ea511f0dcd22bc18fd83
2015-05-13 20:21:07 -07:00
Arve Hjønnevåg
47e06a3f34 [dev][interrupt][arm_gic] Call sm_handle_fiq from platform_fiq
If WITH_LIB_SM is set, call sm_handle_fiq instead of sm_handle_irq
from platform_fiq. This is needed to allow sm_handle_irq to wake up
a thread instead of switching back to ns from the interrupt handler.

Change-Id: Idc728343bc31c07a3149d68730bd57ee28be08f8
2015-05-13 18:08:45 -07:00
Arve Hjønnevåg
5177e5ba40 [dev][interrupt][arm_gic] Enable ns interrupts if WITH_LIB_SM is set
Change-Id: I436b81fe12a969f745ab20cf97500aed1e6f77f7
2015-05-13 18:08:45 -07:00
Arve Hjønnevåg
03d68ec2ae [dev][interrupt][arm_gic] Add trace printf for irq numbers returned to ns
Change-Id: I834ea1861e09edc770f081253a34364e3a8eaeba
2015-05-13 18:08:45 -07:00
Travis Geiselbrecht
f0fad1590b [init][smp] have secondary init run in arch code up to threading, and complete in secondary thread
-move the per-cpu initialization of the gic and cortex-a9 timer into an init hook.
  This removes the hard coded call in arm/arch.c
-make sure the timer initialization happens in the pre-threading callback, in case
  a secondary init hook needs the timer.
2015-03-27 14:14:12 -07:00
Travis Geiselbrecht
ccb073b98b [dev][arm_gic] call the appropriate init routine for secondary cpus coming out of resume 2015-03-27 13:33:58 -07:00
Arve Hjønnevåg
eed6d25ef3 [dev][interrupt][arm_gic] Add arm64 support
Change-Id: I08b1f60af08fe3d8d20a9f85e8e8c03d78aa6aa8
2015-03-19 18:01:12 -07:00
Arve Hjønnevåg
1fe28345a0 [dev][interrupt][arm_gic] Re-initialize gicd registers if needed.
Adds shadow registers so secure interrupt state is restored after suspend.
Adds cpu suspend and resume functions.
Disable fiqs in suspend and re-enable in resume.

Change-Id: Ie4a36d55fdd7275267eeeb208e358ab24855ee64
Signed-off-by: Arve Hjønnevåg <arve@android.com>
2015-03-19 18:01:09 -07:00
Arve Hjønnevåg
615fa16210 [dev][interrupt][arm_gic] Mask all fiqs on fiq entry
Allows multiple fiqs to be registered without one fiq handler
interrupting another and corrupting the return state.

Change-Id: I1ab1bd2e2808d3ff319cc31924e083011ef21fe3
Signed-off-by: Arve Hjønnevåg <arve@android.com>
2015-03-19 18:01:09 -07:00
Arve Hjønnevåg
ba8356d981 [dev][interrupt][arm_gic] Fix normal interrupts after smp rebase
The lk smp branch changed the gic to have per cpu interrupt handlers
for every interrupt. This is not needed for interrupts that are not
cpu specific.

Change-Id: I71298931ec7b337b11934eac2722be254172976e
2015-03-11 19:57:16 -07:00
Travis Geiselbrecht
a6f4e6ff15 [arch][arm] add ARM SMP support
-Also adds support to the following ARM-related drivers:
    dev/cache/pl310
    dev/interrupt/arm_gic
    dev/timer/arm_cortex_a9
2015-03-10 16:43:55 -07:00
Travis Geiselbrecht
a1ce3518bc [platform][zynq] switch to the GIC driver for interrupt controller business 2014-05-01 19:06:50 -07:00
Travis Geiselbrecht
bd118d8a4c [dev][interrupt][arm_gic] add generic gic driver
-This is a flattening of a pile of changes by Arve Hjønnevåg
2014-05-01 19:06:04 -07:00