Disable IO and mem decoding around BAR enumation as described in the PCI
Local Bus specification. This behavior should be safer when messing
around BARs for BAR lengths.
In the case of platforms where a bios or firmware has not already
assigned all the resources, do so. Requires the platform supply one or
more ranges of physical address space and IO that can be mapped into
BARs.
Handles iterating through bridges, computing the sizes of all the
peripherals downstream and rolling that up as well.
Wire them up on arm and riscv which need them. x86-pc does not, so dont
call it.
Also fix a few miscellaneous bugs, notably PCI not detecting 64bit bars
properly due to an off by one bit error.
Had to rearrange the proble logic somewhat, but now the bus manager will
assign consequtive bus numbers as it finds bridges and recursively
drills down to discover the entire bus structure.
Does not assign resources yet, but need to do this in the first pass
to find all of the devices before can figure out how much space they
occupy.
This fixes an infinite recursion where it was stepped into bridge a
bridge that has the secondary bus set to 0, which caused it to start
over and probe bus 0 until it blew the stack.
Better fix is to actually assign busses.
