Travis Geiselbrecht
e739abc490
[kernel] tweak a few thread apis to to take a const pointer
...
A bit of reformatting on some ARM code while was touching it.
2025-10-01 20:56:06 -07:00
Travis Geiselbrecht
902e2fcb8a
WIP set up per cpu structures for x86-64
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only on the boot cpu for now
2024-12-06 21:11:51 -08:00
Travis Geiselbrecht
cba9e47987
[license] replace the longer full MIT license with a shorter one
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Used scripts/replacelic. Everything seems to build fine.
2019-07-05 17:22:23 -07:00
Travis Geiselbrecht
d8fa82cb91
[formatting] run everything through codestyle
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Almost nothing changes here except moving braces to the same line as the
function declaration. Everything else is largely whitespace changes and
a few dangling files with tab indents.
See scripts/codestyle
2019-06-19 21:02:24 -07:00
Travis Geiselbrecht
1b7a28efb8
[include][lk] fixup lk/ include path move
2019-06-19 19:46:11 -07:00
Travis Geiselbrecht
1fbb67228d
[platform][pc] get working on legacy 386 PC
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-Add support for x86 legacy mode, designed for 386+ instead of pentium+
-Fixup uart driver to support com2
-Stub out PCI driver properly
-Fixup IDE driver to detect legacy disks
2018-12-30 21:08:58 -08:00
Travis Geiselbrecht
ee672a5471
[arch][x86] flatten x86-64 and x86 into a single tree of code
...
Major refactor of x86 code into a single arch.
Also bump both 32 and 64 bit to running the kernel at a 'high' address.
2016-02-29 12:42:45 -08:00
Zhu, Bing
6216532654
[arch][x86][x64][fpu]fix compile failure when X86_WITH_FPU is not defined.
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With this patch, no compile failure issue when either X86_WITH_FPU not defined
or defined as 0(1).
Signed-off-by: Zhu, Bing <bing.zhu@intel.com >
2015-11-25 13:36:04 -08:00
Zhu, Bing
b6647f5bef
[arch][x86][fpu]Change naming convention for FPU flag
...
To align with lk/arm flag naming convention, FPU flag
ENABLE_FPU is changed to X86_WITH_FPU
Signed-off-by: Zhu, Bing <bing.zhu@intel.com >
2015-11-09 22:14:11 +08:00
Travis Geiselbrecht
853c436ea3
[arch][x86] mass-reformat to space indents on all the x86 and x86-64 files
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used scripts/codestyle.space
2015-11-06 19:32:51 -08:00
Travis Geiselbrecht
d394f5b83f
[arch][x86] fix a few warnings in x86 code
2015-10-27 13:17:50 -07:00
yu-cheng yu
0400a04945
[arch][x86] This is floating point support for intel x86 and x86-64.
...
Change-Id: Id0b0e2b69c1d27832eb656935e944c04681b324a
2015-10-27 13:04:45 -07:00
Travis Geiselbrecht
45d56cc2e1
[arch][x86] get x86 building and working again after SMP changes
...
-Add UP spinlock routines and irq save/restore
-fix platform/pc drivers to use spinlocks instead of critical_section
2015-03-10 16:43:55 -07:00
Travis Geiselbrecht
a99a962333
[arch] update all the arches to implement get_current_thread()
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-For ARM and ARM64, use the cpu local registers
-for X86, X86-64, and ARM-M, use a global variable
2014-05-03 23:58:50 -07:00
Travis Geiselbrecht
5c1df88168
[arch] run astyle on arch/
2012-10-31 21:52:16 -07:00
Corey Tabaka
d4427fa54c
Initial x86 port
2009-04-24 11:14:38 -07:00
