7 Commits

Author SHA1 Message Date
Travis Geiselbrecht
936ee8ac81 [arch][x86] start of an ioapic driver
Doesn't do much but provided the detection path for it and ability to
hold initialized state. The higher level platform code is going to need
to use it directly so will mostly just provide an api for access to it.

Moved ACPI sniffing back to just after the VM is initialized instead of
all the way into platform_init(). This should try to ensure that all
drivers that come up afterwards will have ioapics discovered in case
future development tries to enable and use them, kicking the machine out
of virtual-wire-mode.
2025-09-24 01:18:52 -07:00
Travis Geiselbrecht
b7d69d8804 [arch][x86] handle the local apic of the boot cpu not being 0
I have a bulldozer machine here that curiously starts the APIC IDs for
the cpus at 16 and counts up.

This is a problem since the current code assumes that the boot cpu is 0,
and would try to start itself (apic id 16) later because it thought it
was the first secondary. Fix this by re-reading the APIC id on the boot
cpu and patching the percpu structure a bit into boot. Kinda a hack but
avoids having to detect the APIC, find the type of ID to read, etc.

Also means that practically speaking the system is using the full 32bit
APIC IDs if that feature is present, since now the local apic id is
entirely read from the local apic as it should be (if present).

Fixes #475
2025-09-22 20:57:30 -07:00
Travis Geiselbrecht
bdf2203fdc [arch][x86][lapic] a little bit of restructuring of some recent lapic code
Functionally equivalent, but refactor two copies of local apic
initialization code into a shared routine.
2025-09-21 21:53:35 -07:00
little fairy
d0eb5c464e [arch][x86] Read full 32bit apic id from x2apic msr if available (#465) 2025-09-21 21:04:00 -07:00
Travis Geiselbrecht
699ec6344e [arch][x86][smp] few misc tweaks
- Skip cpus in the MADT table that are not enabled
- Bump count to 16 cpus
- Move the spurious interrupt vector to 0xff since it needs to end in
  0xf on <=P6.
2025-04-06 22:22:20 -07:00
Travis Geiselbrecht
a8bc048648 [arch][x86] tighten up x86 cpu bootstrap code
- Fix an assert in local apic code when not using x2apic and starting
  secondaries.
- Follow the spec a bit closer and wait up till a second for each
  secondary core to start.
2025-04-06 21:13:06 -07:00
Travis Geiselbrecht
5a520eca3e [arch][x86] start getting inter-processor-interrupts working
-Move the local apic driver to arch/x86
-Add routines to send IPIs between cpus

Something is unstable at the moment and the system crashes after a while
with random corruptions when using SMP.
2025-04-01 00:40:50 -07:00