18 Commits

Author SHA1 Message Date
Travis Geiselbrecht
5016118509 [fpu] have the arch layers set WITH_NO_FPU based on the cpu
This will generally turn off more FPU codegen, even if its using
software fallback unless the project/target/platform selects a cpu that
has FPU support. This also turns off a few blocks of test code and the
upcoming floating point printf if it's not present on the arch.

This may break projects that were compiling for say cortex-m0 but
expected FPU code to be present. If so it should be pretty easy to
override it, but not going to add that yet unless it's necessary.
2025-10-08 23:50:53 -07:00
Travis Geiselbrecht
ad6ef65a5a [arch][ops.h] force all of the fast routines to be inline
Also make sure each arch_ops.h always includes arch/ops.h at the top, to
make sure the declaration always appears in front of the definition.
2025-10-01 20:56:07 -07:00
Travis Geiselbrecht
e739abc490 [kernel] tweak a few thread apis to to take a const pointer
A bit of reformatting on some ARM code while was touching it.
2025-10-01 20:56:06 -07:00
Lei Wen
145e9a0d27 [arch] fix link script not include global array init
Using wild match init_array* to include global array init ctor

Before:

 10 .ctors             00000040 ffff0000001e6b80 00000000401e6b80 DATA
 11 .dtors             00000000 ffff0000001e6bc0 00000000401e6bc0 DATA
 12 .got               00000060 ffff0000001e6bc0 00000000401e6bc0 DATA
 13 .init_array.1      00000470 ffff0000001e6c20 00000000401e6c20
 14 .fini_array.1      00000470 ffff0000001e7090 00000000401e7090
 15 .dummy_post_data   00000000 ffff0000001e7500 00000000401e7500 DATA
 16 .bss               00009460 ffff0000001e8000 00000000401e8000 BSS

After:

 10 .ctors             000004b0 ffff0000001e6b80 00000000401e6b80 DATA
 11 .dtors             00000470 ffff0000001e7030 00000000401e7030
 12 .got               00000060 ffff0000001e74a0 00000000401e74a0 DATA
 13 .dummy_post_data   00000000 ffff0000001e7500 00000000401e7500 DATA
 14 .bss               00009460 ffff0000001e8000 00000000401e8000 BSS

Signed-off-by: Lei Wen <leiwen@asrmicro.com>
2025-09-29 22:40:41 -07:00
Travis Geiselbrecht
cc9c3a053c [arch][mmu] clean up page size definitions in each arch's defines.h
No real functional change except how the smaller ARCH_DEFAULT_PAGE_SIZE
is now computed and set in defines.h instead of rules.mk for arch/arm to
be consistent with the other arch that has a large/small build (riscv).
2025-08-31 19:16:58 -07:00
Travis Geiselbrecht
e31b1ee768 [arch][m68k] make sure move %sp, <reg> doesn't use the 'a' registers
This particular instruction format doesn't take plain a registers, but
takes d and the rest of the <ea> formats.
2025-05-06 23:26:10 -07:00
Travis Geiselbrecht
86267ca23c [include][reg.h] define new mmio_read/write accessors
To work properly with some hypervisors on various architectures (ARM,
ARM64, x86), add global routines to allow access to MMIO registers via
architecturally defined accessors.

Add accessors for ARM, ARM64, and x86-32/64. Have the other arches
default to just using whatever the compiler emits.

Will need to generally move things off the legacy REG*() accessors
since they're really not safe going forward with what compilers emit.
2024-05-13 00:39:29 -07:00
Travis Geiselbrecht
339ff8995a [arch][barriers] add default memory barriers for all of the architectures
Most are pretty straightforward, but a few of the more esoteric
architectures just defaults are implemented.
2024-05-09 19:51:32 -07:00
Travis Geiselbrecht
7e11c3bf78 [arch][m68k] save up to 4 arguments passed to LK
Pass the first 4 words on the stack that may have been passed from
firmware or bootloader to LK on to lk_main.
2024-02-11 00:38:52 -08:00
Travis Geiselbrecht
479d989185 [make] default WITH_LINKER_GC to false at the place it is used
Also switch the test logic to the TOBOOL macro.
2022-04-18 01:15:45 -07:00
Travis Geiselbrecht
8028512833 [arch][m68k] add more switches for cpu models 2022-04-12 17:26:33 -07:00
Travis Geiselbrecht
49644a2c39 [platform][rosco-m68k] Add port to the Rosco M68k board
Port to the really neat 68010 based board at https://rosco-m68k.com/

Port Features:
-10Mhz 68010
-1MB ram
-Dual UART + timer implemented as a 68c681 chip
-timer running at 1Khz, UART A for console
-interrupt driven RX support

Some amount of extending of the 68k exceptinon code was needed to
support the autovectored irqs that the 68681 uart uses. Added build
system support for 68010.
2022-04-12 00:25:12 -07:00
Travis Geiselbrecht
cc21c06eb6 [platform][m68k-virt] parse the BOOTINFO structure qemu uses to pass info
Pull out the memory size of the system and use it to initialize the
novm.
2022-02-11 00:37:51 -08:00
Travis Geiselbrecht
4b508cecc9 [arch][m68k] use a jsr in the initial start routine to main
It's non ideal, since there's no relaxation done in the linker so we
have to assume the branch target is > 16 bits away and do what the
compiler usually does and emit a full 32bit jsr.
2021-06-11 21:34:34 -07:00
Travis Geiselbrecht
bd12570f3c [arch][m68k] fix and optimize interrupt disable/enable/restore
Mostly rewrote to be cleaner and more obvious what it's doing, but turns
out the real problem was a lack of "memory" and/or volatile. In one of
the test cases the compiler was rearranging the arch_ints_disabled()
check.
2021-06-11 21:14:22 -07:00
Travis Geiselbrecht
0d721ca245 [arch][m68k] add idle loop 2021-06-11 21:13:56 -07:00
Travis Geiselbrecht
d6fa4d5b80 [arch][m68k] add exception and irq processing
-Add interrupt controller and timer support for qemu virt machine
-Switch tty read to irq driven as well
2021-06-07 02:40:02 -07:00
Travis Geiselbrecht
12fee4b59a [arch][m68k] initial port to m68k
Uses the QEMU virt machine for 68k defined in qemu 6.0+.
Basic support that boots, prints to the console, takes input from
console, and context switches.

TODO: interrupt support, timer support.
2021-06-06 19:38:45 -07:00