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[zynq] Add MIO_DEFAULT and correctly ignore MIO configuration based on that rather than 0

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This commit is contained in:
Christopher Anderson
2015-04-01 14:33:49 -07:00
parent f0fbbe0550
commit ffbb7b8fd3
3 changed files with 16 additions and 1 deletions
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2
platform/zynq/include/platform/zynq.h
View File

@@ -476,6 +476,8 @@ STATIC_ASSERT(offsetof(struct slcr_regs, DDRIOB_DCI_STATUS) == 0xb74);
#define MIO_IO_TYPE_HSTL (0x4 << 9)
#define MIO_PULLUP (1 << 12)
#define MIO_DISABLE_RCVR (1 << 13)
#define MIO_GPIO (MIO_IO_TYPE_LVCMOS18 | MIO_DISABLE_RCVR)
#define MIO_DEFAULT (0xFFFF0000)
/* UART registers */
#define UART_CR (0x00)

2
platform/zynq/platform.c
View File

@@ -123,7 +123,7 @@ int zynq_mio_init(void)
SLCR_REG(GPIOB_CTRL) = GPIOB_CTRL_VREF_EN;
for (size_t pin = 0; pin < countof(zynq_mio_cfg); pin++) {
if (zynq_mio_cfg[pin] != 0) {
if (zynq_mio_cfg[pin] != MIO_DEFAULT) {
SLCR_REG(MIO_PIN_00 + (pin * 4)) = zynq_mio_cfg[pin];
}
}

13
target/zybo/target.c
View File

@@ -89,14 +89,24 @@ const zynq_ddriob_cfg_t zynq_ddriob_cfg = {
};
const uint32_t zynq_mio_cfg[ZYNQ_MIO_CNT] = {
[0] = MIO_DEFAULT,
[1] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33,
[2] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33,
[3] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33,
[4] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33,
[5] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33,
[6] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33,
// LED4
[7] = MIO_GPIO,
[8] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33,
// 16-21 gem0
[9] = MIO_DEFAULT,
[10] = MIO_DEFAULT,
[11] = MIO_DEFAULT,
[12] = MIO_DEFAULT,
[13] = MIO_DEFAULT,
[14] = MIO_DEFAULT,
[15] = MIO_DEFAULT,
[16] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_PULLUP | MIO_DISABLE_RCVR,
[17] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_PULLUP | MIO_DISABLE_RCVR,
[18] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_PULLUP | MIO_DISABLE_RCVR,
@@ -131,6 +141,9 @@ const uint32_t zynq_mio_cfg[ZYNQ_MIO_CNT] = {
[47] = MIO_TRI_ENABLE | MIO_IO_TYPE_LVCMOS18,
[48] = MIO_L3_SEL(0x7) | MIO_IO_TYPE_LVCMOS18,
[49] = MIO_TRI_ENABLE | MIO_L3_SEL(0x7) | MIO_IO_TYPE_LVCMOS18,
// 50-51 are BTN4 and BTN5
[50] = MIO_GPIO,
[51] = MIO_GPIO,
// 52-53 gem0
[52] = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18 | MIO_PULLUP,
[53] = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18 | MIO_PULLUP,