diff --git a/platform/zynq/include/platform/zynq.h b/platform/zynq/include/platform/zynq.h
index 4562253e..d9309831 100644
--- a/platform/zynq/include/platform/zynq.h
+++ b/platform/zynq/include/platform/zynq.h
@@ -476,6 +476,8 @@ STATIC_ASSERT(offsetof(struct slcr_regs, DDRIOB_DCI_STATUS) == 0xb74);
 #define MIO_IO_TYPE_HSTL                (0x4 << 9)
 #define MIO_PULLUP                      (1 << 12)
 #define MIO_DISABLE_RCVR                (1 << 13)
+#define MIO_GPIO                        (MIO_IO_TYPE_LVCMOS18 | MIO_DISABLE_RCVR)
+#define MIO_DEFAULT                     (0xFFFF0000)
 
 /* UART registers */
 #define UART_CR                         (0x00)
diff --git a/platform/zynq/platform.c b/platform/zynq/platform.c
index 23d501ee..b9188b95 100644
--- a/platform/zynq/platform.c
+++ b/platform/zynq/platform.c
@@ -123,7 +123,7 @@ int zynq_mio_init(void)
     SLCR_REG(GPIOB_CTRL) = GPIOB_CTRL_VREF_EN;
 
     for (size_t pin = 0; pin < countof(zynq_mio_cfg); pin++) {
-        if (zynq_mio_cfg[pin] != 0) {
+        if (zynq_mio_cfg[pin] != MIO_DEFAULT) {
             SLCR_REG(MIO_PIN_00 + (pin * 4)) = zynq_mio_cfg[pin];
         }
     }
diff --git a/target/zybo/target.c b/target/zybo/target.c
index 7ac04ce8..1e148daa 100644
--- a/target/zybo/target.c
+++ b/target/zybo/target.c
@@ -89,14 +89,24 @@ const zynq_ddriob_cfg_t zynq_ddriob_cfg = {
 };
 
 const uint32_t zynq_mio_cfg[ZYNQ_MIO_CNT] = {
+    [0] = MIO_DEFAULT,
     [1] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33,
     [2] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33,
     [3] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33,
     [4] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33,
     [5] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33,
     [6] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33,
+    // LED4
+    [7] = MIO_GPIO,
     [8] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33,
     // 16-21 gem0
+    [9] = MIO_DEFAULT,
+    [10] = MIO_DEFAULT,
+    [11] = MIO_DEFAULT,
+    [12] = MIO_DEFAULT,
+    [13] = MIO_DEFAULT,
+    [14] = MIO_DEFAULT,
+    [15] = MIO_DEFAULT,
     [16] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_PULLUP | MIO_DISABLE_RCVR,
     [17] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_PULLUP | MIO_DISABLE_RCVR,
     [18] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_PULLUP | MIO_DISABLE_RCVR,
@@ -131,6 +141,9 @@ const uint32_t zynq_mio_cfg[ZYNQ_MIO_CNT] = {
     [47] = MIO_TRI_ENABLE | MIO_IO_TYPE_LVCMOS18,
     [48] = MIO_L3_SEL(0x7) | MIO_IO_TYPE_LVCMOS18,
     [49] = MIO_TRI_ENABLE | MIO_L3_SEL(0x7) | MIO_IO_TYPE_LVCMOS18,
+    // 50-51 are BTN4 and BTN5
+    [50] = MIO_GPIO,
+    [51] = MIO_GPIO,
     // 52-53 gem0
     [52] = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18 | MIO_PULLUP,
     [53] = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18 | MIO_PULLUP,