diff --git a/app/tests/thread_tests.c b/app/tests/thread_tests.c
index 27a8c247..97f8289a 100644
--- a/app/tests/thread_tests.c
+++ b/app/tests/thread_tests.c
@@ -17,6 +17,7 @@
 #include <kernel/semaphore.h>
 #include <kernel/event.h>
 #include <platform.h>
+#include <arch/atomic.h>
 
 static int sleep_thread(void *arg) {
     for (;;) {
diff --git a/arch/arm/arm/arch.c b/arch/arm/arm/arch.c
index ce955c01..09362258 100644
--- a/arch/arm/arm/arch.c
+++ b/arch/arm/arm/arch.c
@@ -13,6 +13,7 @@
 #include <stdio.h>
 #include <lk/reg.h>
 #include <arch.h>
+#include <arch/atomic.h>
 #include <arch/ops.h>
 #include <arch/mmu.h>
 #include <arch/arm.h>
diff --git a/arch/arm/include/arch/arch_atomic.h b/arch/arm/include/arch/arch_atomic.h
new file mode 100644
index 00000000..7dd8da1b
--- /dev/null
+++ b/arch/arm/include/arch/arch_atomic.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2008-2014 Travis Geiselbrecht
+ *
+ * Use of this source code is governed by a MIT-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/MIT
+ */
+#pragma once
+
+#include <arch/ops.h>
+
+// define simple implementations of the atomic routines for these cpus
+// that do not otherwise have an implementation.
+#if !USE_BUILTIN_ATOMICS
+#if ARM_ISA_ARMV6M // cortex-m0 cortex-m0+
+
+static inline int atomic_add(volatile int *ptr, int val) {
+    int temp;
+    bool state;
+
+    state = arch_ints_disabled();
+    arch_disable_ints();
+    temp = *ptr;
+    *ptr = temp + val;
+    if (!state)
+        arch_enable_ints();
+    return temp;
+}
+
+static inline  int atomic_and(volatile int *ptr, int val) {
+    int temp;
+    bool state;
+
+    state = arch_ints_disabled();
+    arch_disable_ints();
+    temp = *ptr;
+    *ptr = temp & val;
+    if (!state)
+        arch_enable_ints();
+    return temp;
+}
+
+static inline int atomic_or(volatile int *ptr, int val) {
+    int temp;
+    bool state;
+
+    state = arch_ints_disabled();
+    arch_disable_ints();
+    temp = *ptr;
+    *ptr = temp | val;
+    if (!state)
+        arch_enable_ints();
+    return temp;
+}
+
+static inline int atomic_swap(volatile int *ptr, int val) {
+    int temp;
+    bool state;
+
+    state = arch_ints_disabled();
+    arch_disable_ints();
+    temp = *ptr;
+    *ptr = val;
+    if (!state)
+        arch_enable_ints();
+    return temp;
+}
+
+static inline int atomic_cmpxchg(volatile int *ptr, int oldval, int newval) {
+    int temp;
+    bool state;
+
+    state = arch_ints_disabled();
+    arch_disable_ints();
+    temp = *ptr;
+    if (temp == oldval) {
+        *ptr = newval;
+    }
+    if (!state)
+        arch_enable_ints();
+    return temp;
+}
+
+#endif // ARM_ISA_ARMV6M
+#endif // !USE_BUILTIN_ATOMICS
diff --git a/arch/arm/include/arch/arch_ops.h b/arch/arm/include/arch/arch_ops.h
index bb252ac0..90e287d3 100644
--- a/arch/arm/include/arch/arch_ops.h
+++ b/arch/arm/include/arch/arch_ops.h
@@ -159,8 +159,6 @@ static inline bool arch_fiqs_disabled(void) {
     return !!state;
 }
 
-
-
 static inline void arch_enable_ints(void) {
     CF;
     __asm__ volatile("cpsie i");
@@ -178,73 +176,6 @@ static inline bool arch_ints_disabled(void) {
     return !!state;
 }
 
-static inline int atomic_add(volatile int *ptr, int val) {
-    int temp;
-    bool state;
-
-    state = arch_ints_disabled();
-    arch_disable_ints();
-    temp = *ptr;
-    *ptr = temp + val;
-    if (!state)
-        arch_enable_ints();
-    return temp;
-}
-
-static inline  int atomic_and(volatile int *ptr, int val) {
-    int temp;
-    bool state;
-
-    state = arch_ints_disabled();
-    arch_disable_ints();
-    temp = *ptr;
-    *ptr = temp & val;
-    if (!state)
-        arch_enable_ints();
-    return temp;
-}
-
-static inline int atomic_or(volatile int *ptr, int val) {
-    int temp;
-    bool state;
-
-    state = arch_ints_disabled();
-    arch_disable_ints();
-    temp = *ptr;
-    *ptr = temp | val;
-    if (!state)
-        arch_enable_ints();
-    return temp;
-}
-
-static inline int atomic_swap(volatile int *ptr, int val) {
-    int temp;
-    bool state;
-
-    state = arch_ints_disabled();
-    arch_disable_ints();
-    temp = *ptr;
-    *ptr = val;
-    if (!state)
-        arch_enable_ints();
-    return temp;
-}
-
-static inline int atomic_cmpxchg(volatile int *ptr, int oldval, int newval) {
-    int temp;
-    bool state;
-
-    state = arch_ints_disabled();
-    arch_disable_ints();
-    temp = *ptr;
-    if (temp == oldval) {
-        *ptr = newval;
-    }
-    if (!state)
-        arch_enable_ints();
-    return temp;
-}
-
 static inline uint32_t arch_cycle_count(void) {
     return 0;
 }
diff --git a/arch/arm64/arch.c b/arch/arm64/arch.c
index 1d6e66bd..0111e3ae 100644
--- a/arch/arm64/arch.c
+++ b/arch/arm64/arch.c
@@ -8,6 +8,7 @@
 #include <lk/debug.h>
 #include <stdlib.h>
 #include <arch.h>
+#include <arch/atomic.h>
 #include <arch/ops.h>
 #include <arch/arm64.h>
 #include <arch/arm64/mmu.h>
diff --git a/arch/include/arch/atomic.h b/arch/include/arch/atomic.h
new file mode 100644
index 00000000..e9887208
--- /dev/null
+++ b/arch/include/arch/atomic.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2008-2014 Travis Geiselbrecht
+ *
+ * Use of this source code is governed by a MIT-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/MIT
+ */
+#pragma once
+
+#include <lk/compiler.h>
+#include <stdbool.h>
+
+__BEGIN_CDECLS
+
+/* use built in atomic intrinsics if the architecture doesn't otherwise
+ * override it. */
+#if !defined(USE_BUILTIN_ATOMICS) || USE_BUILTIN_ATOMICS
+static inline int atomic_add(volatile int *ptr, int val) {
+    return __atomic_fetch_add(ptr, val, __ATOMIC_RELAXED);
+}
+
+static inline int atomic_or(volatile int *ptr, int val) {
+    return __atomic_fetch_or(ptr, val, __ATOMIC_RELAXED);
+}
+
+static inline int atomic_and(volatile int *ptr, int val) {
+    return __atomic_fetch_and(ptr, val, __ATOMIC_RELAXED);
+}
+
+static inline int atomic_swap(volatile int *ptr, int val) {
+    return __atomic_exchange_n(ptr, val, __ATOMIC_RELAXED);
+}
+static inline int atomic_cmpxchg(volatile int *ptr, int oldval, int newval) {
+    // TODO: implement
+    return 0;
+}
+
+#else
+static int atomic_swap(volatile int *ptr, int val);
+static int atomic_add(volatile int *ptr, int val);
+static int atomic_and(volatile int *ptr, int val);
+static int atomic_or(volatile int *ptr, int val);
+
+/* if an implementation wants to implement it themselves */
+#include <arch/arch_atomic.h>
+
+#endif
+
diff --git a/arch/include/arch/ops.h b/arch/include/arch/ops.h
index 08f48c6d..000df74f 100644
--- a/arch/include/arch/ops.h
+++ b/arch/include/arch/ops.h
@@ -22,36 +22,6 @@ static void arch_disable_ints(void);
 static bool arch_ints_disabled(void);
 static bool arch_in_int_handler(void);
 
-/* use built in atomic intrinsics if the architecture doesn't otherwise
- * override it. */
-#if !defined(USE_BUILTIN_ATOMICS) || USE_BUILTIN_ATOMICS
-static inline int atomic_add(volatile int *ptr, int val) {
-    return __atomic_fetch_add(ptr, val, __ATOMIC_RELAXED);
-}
-
-static inline int atomic_or(volatile int *ptr, int val) {
-    return __atomic_fetch_or(ptr, val, __ATOMIC_RELAXED);
-}
-
-static inline int atomic_and(volatile int *ptr, int val) {
-    return __atomic_fetch_and(ptr, val, __ATOMIC_RELAXED);
-}
-
-static inline int atomic_swap(volatile int *ptr, int val) {
-    return __atomic_exchange_n(ptr, val, __ATOMIC_RELAXED);
-}
-static inline int atomic_cmpxchg(volatile int *ptr, int oldval, int newval) {
-    // TODO: implement
-    return 0;
-}
-
-#else
-static int atomic_swap(volatile int *ptr, int val);
-static int atomic_add(volatile int *ptr, int val);
-static int atomic_and(volatile int *ptr, int val);
-static int atomic_or(volatile int *ptr, int val);
-#endif
-
 static uint32_t arch_cycle_count(void);
 
 static uint arch_curr_cpu_num(void);
diff --git a/arch/riscv/mp.c b/arch/riscv/mp.c
index 7f06909b..887cf5f9 100644
--- a/arch/riscv/mp.c
+++ b/arch/riscv/mp.c
@@ -15,6 +15,7 @@
 #include <lk/init.h>
 #include <lk/main.h>
 
+#include <arch/atomic.h>
 #include <arch/ops.h>
 #include <arch/mp.h>
 #include <arch/riscv/clint.h>
diff --git a/external/lib/lwip/netif.c b/external/lib/lwip/netif.c
index b8e9f79b..a94023cc 100644
--- a/external/lib/lwip/netif.c
+++ b/external/lib/lwip/netif.c
@@ -1,5 +1,6 @@
 #include <dev/class/netif.h>
 #include <kernel/event.h>
+#include <arch/atomic.h>
 #include <arch/ops.h>
 #include <netif/etharp.h>
 #include <lwip/netif.h>
diff --git a/kernel/mp.c b/kernel/mp.c
index a5d72471..0787cab8 100644
--- a/kernel/mp.c
+++ b/kernel/mp.c
@@ -8,6 +8,7 @@
 
 #include <kernel/mp.h>
 
+#include <arch/atomic.h>
 #include <arch/mp.h>
 #include <assert.h>
 #include <kernel/spinlock.h>
diff --git a/lib/bio/bio.c b/lib/bio/bio.c
index b712deaf..d11165bd 100644
--- a/lib/bio/bio.c
+++ b/lib/bio/bio.c
@@ -5,6 +5,8 @@
  * license that can be found in the LICENSE file or at
  * https://opensource.org/licenses/MIT
  */
+#include <lib/bio.h>
+
 #include <stdlib.h>
 #include <lk/debug.h>
 #include <lk/trace.h>
@@ -13,9 +15,9 @@
 #include <assert.h>
 #include <lk/list.h>
 #include <lk/pow2.h>
-#include <lib/bio.h>
 #include <kernel/mutex.h>
 #include <lk/init.h>
+#include <arch/atomic.h>
 
 #define LOCAL_TRACE 0
 
diff --git a/lib/minip/tcp.c b/lib/minip/tcp.c
index 05e489bc..9d7da2e9 100644
--- a/lib/minip/tcp.c
+++ b/lib/minip/tcp.c
@@ -21,6 +21,7 @@
 #include <kernel/semaphore.h>
 #include <arch/ops.h>
 #include <platform.h>
+#include <arch/atomic.h>
 
 #define LOCAL_TRACE 0
 
diff --git a/top/include/lk/bits.h b/top/include/lk/bits.h
index 3ec846e9..e2ad2a89 100644
--- a/top/include/lk/bits.h
+++ b/top/include/lk/bits.h
@@ -7,6 +7,7 @@
  */
 #pragma once
 
+#include <arch/atomic.h>
 #include <arch/ops.h>
 #include <lk/compiler.h>