[bus][pci] Support for dynamically assigning BARs and bridges if needed

In the case of platforms where a bios or firmware has not already
assigned all the resources, do so. Requires the platform supply one or
more ranges of physical address space and IO that can be mapped into
BARs.

Handles iterating through bridges, computing the sizes of all the
peripherals downstream and rolling that up as well.

dev/interrupt/arm_gic/arm_gic.c

@@ -105,7 +105,10 @@ void register_int_handler(unsigned int vector, int_handler handler, void *arg) {
 }
 
 void register_int_handler_msi(unsigned int vector, int_handler handler, void *arg, bool edge) {
-    PANIC_UNIMPLEMENTED;
+    // only can deal with edge triggered at the moment
+    DEBUG_ASSERT(edge);
+
+    register_int_handler(vector, handler, arg);
 }
 
 #define GICREG(gic, reg) (*REG32(GICBASE(gic) + (reg)))