diff --git a/project/zybo.mk b/project/zybo.mk
new file mode 100644
index 00000000..f48a13c7
--- /dev/null
+++ b/project/zybo.mk
@@ -0,0 +1,13 @@
+# top level project rules for the armemu-test project
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+TARGET := zybo
+
+MODULES += \
+	app/tests \
+	app/stringtests \
+	app/shell \
+	lib/debugcommands
+
+
diff --git a/target/zybo/include/target/debugconfig.h b/target/zybo/include/target/debugconfig.h
new file mode 100644
index 00000000..3c74bc5e
--- /dev/null
+++ b/target/zybo/include/target/debugconfig.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2014 Travis Geiselbrecht
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#define DEBUG_UART 1
diff --git a/target/zybo/init.c b/target/zybo/init.c
new file mode 100644
index 00000000..5b6a7860
--- /dev/null
+++ b/target/zybo/init.c
@@ -0,0 +1,455 @@
+/*
+* This file is automatically generated
+*/
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
+#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask)     ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
+#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
+
+/* Freq of all peripherals */
+#define APU_FREQ  650000000
+#define DDR_FREQ  525000000
+#define DCI_FREQ  10159000
+#define QSPI_FREQ  200000000
+#define SMC_FREQ  100000000
+#define ENET0_FREQ  125000000
+#define ENET1_FREQ  125000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  50000000
+#define UART_FREQ  50000000
+#define SPI_FREQ  166666666
+#define I2C_FREQ  108333336
+#define WDT_FREQ  133333333
+#define TTC_FREQ  50000000
+#define CAN_FREQ  100000000
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  100000000
+#define FPGA1_FREQ  175000000
+#define FPGA2_FREQ  12288000
+#define FPGA3_FREQ  100000000
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32  0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32  0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL    0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC   0xF8F00218
+
+static void perf_start_clock(void);
+static void perf_disable_clock(void);
+static void perf_reset_clock(void);
+static void perf_reset_and_start_timer(void);
+static unsigned int get_number_of_cycles_for_delay(unsigned int delay);
+
+static const unsigned long ps7_pll_init_data_3_0[] = {
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001772C0U),
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001A000U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001DB2C0U),
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00015000U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001F42C0U),
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00014000U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    EMIT_EXIT(),
+};
+
+static const unsigned long ps7_clock_init_data_3_0[] = {
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203401U),
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100630U),
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00203520U),
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100A00U),
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    EMIT_EXIT(),
+};
+
+static const unsigned long ps7_ddr_init_data_3_0[] = {
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x0000107FU),
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004151AU),
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E354D2U),
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011014U),
+    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
+    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0670C845U),
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023C00U),
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00022800U),
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00022C00U),
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00024800U),
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU),
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU),
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000075U),
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E4U),
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000DFU),
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E0U),
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E7U),
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU),
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU),
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B5U),
+    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A6U),
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    EMIT_EXIT(),
+};
+
+static const unsigned long ps7_mio_init_data_3_0[] = {
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E60U),
+    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U),
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002902U),
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002902U),
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002902U),
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002902U),
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002902U),
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002902U),
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000903U),
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000903U),
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000903U),
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000903U),
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000903U),
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000903U),
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
+    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    EMIT_EXIT(),
+};
+
+static const unsigned long ps7_peripherals_init_data_3_0[] = {
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    EMIT_EXIT(),
+};
+
+static const unsigned long ps7_post_config_3_0[] = {
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    EMIT_EXIT(),
+};
+
+#define PS7_MASK_POLL_TIME 100000000
+
+static void mask_write(unsigned long add, unsigned long  mask, unsigned long val)
+{
+    unsigned long *addr = (unsigned long*) add;
+    *addr = (val & mask)|(*addr & ~mask);
+}
+
+static int mask_poll(unsigned long add, unsigned long mask)
+{
+    unsigned long *addr = (unsigned long*) add;
+    int i = 0;
+    while (!(*addr & mask)) {
+        if (i == PS7_MASK_POLL_TIME) {
+            return -1;
+        }
+        i++;
+    }
+    return 1;
+}
+
+static unsigned long mask_read(unsigned long add, unsigned long mask)
+{
+    unsigned long *addr = (unsigned long*) add;
+    unsigned long val = (*addr & mask);
+    return val;
+}
+
+static int ps7_config(const unsigned long *ps7_config_init)
+{
+    const unsigned long *ptr = ps7_config_init;
+
+    int finish = -1;
+    while ( finish < 0 ) {
+        volatile unsigned long *addr;
+        unsigned long val;
+        unsigned long mask;
+
+        int numargs = ptr[0] & 0xF;
+        unsigned long opcode = ptr[0] >> 4;
+
+        unsigned long args[16];
+        for (int j = 0 ; j < numargs ; j++)
+            args[j] = ptr[j+1];
+        ptr += numargs + 1;
+
+        switch ( opcode ) {
+
+            case OPCODE_EXIT:
+                finish = PS7_INIT_SUCCESS;
+                break;
+
+            case OPCODE_CLEAR:
+                addr = (unsigned long*) args[0];
+                *addr = 0;
+                break;
+
+            case OPCODE_WRITE:
+                addr = (unsigned long*) args[0];
+                val = args[1];
+                *addr = val;
+                break;
+
+            case OPCODE_MASKWRITE:
+                addr = (unsigned long*) args[0];
+                mask = args[1];
+                val = args[2];
+                *addr = ( val & mask ) | ( *addr & ~mask);
+                break;
+
+            case OPCODE_MASKPOLL:
+                addr = (unsigned long*) args[0];
+                mask = args[1];
+                int i = 0;
+                while (!(*addr & mask)) {
+                    if (i == PS7_MASK_POLL_TIME) {
+                        finish = PS7_INIT_TIMEOUT;
+                        break;
+                    }
+                    i++;
+                }
+                break;
+            case OPCODE_MASKDELAY:
+                addr = (unsigned long*) args[0];
+                mask = args[1];
+                unsigned int delay = get_number_of_cycles_for_delay(mask);
+                perf_reset_and_start_timer();
+                while ((*addr < delay))
+                    ;
+                break;
+            default:
+                finish = PS7_INIT_CORRUPT;
+                break;
+        }
+    }
+    return finish;
+}
+
+int ps7_init(void)
+{
+    int ret;
+
+    // MIO init
+    ret = ps7_config (ps7_mio_init_data_3_0);
+    if (ret != PS7_INIT_SUCCESS) return ret;
+
+    // PLL init
+    ret = ps7_config (ps7_pll_init_data_3_0);
+    if (ret != PS7_INIT_SUCCESS) return ret;
+
+    // Clock init
+    ret = ps7_config (ps7_clock_init_data_3_0);
+    if (ret != PS7_INIT_SUCCESS) return ret;
+
+    // DDR init
+    ret = ps7_config (ps7_ddr_init_data_3_0);
+    if (ret != PS7_INIT_SUCCESS) return ret;
+
+    // Peripherals init
+    ret = ps7_config (ps7_peripherals_init_data_3_0);
+    if (ret != PS7_INIT_SUCCESS) return ret;
+
+    // post config
+    ret = ps7_config (ps7_post_config_3_0);
+    if (ret != PS7_INIT_SUCCESS) return ret;
+
+    return PS7_INIT_SUCCESS;
+}
+
+/* For delay calculation using global timer */
+
+/* start timer */
+static void perf_start_clock(void)
+{
+    *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
+            (1 << 3) | // Auto-increment
+            (0 << 8) // Pre-scale
+            );
+}
+
+/* stop timer and reset timer count regs */
+static void perf_reset_clock(void)
+{
+    perf_disable_clock();
+    *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+    *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+static unsigned int get_number_of_cycles_for_delay(unsigned int delay)
+{
+    // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+    return (APU_FREQ*delay/(2*1000));
+}
+
+/* stop timer */
+static void perf_disable_clock(void)
+{
+    *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+static void perf_reset_and_start_timer(void)
+{
+    perf_reset_clock();
+    perf_start_clock();
+}
+
+
diff --git a/target/zybo/rules.mk b/target/zybo/rules.mk
new file mode 100644
index 00000000..c48dc867
--- /dev/null
+++ b/target/zybo/rules.mk
@@ -0,0 +1,19 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+MODULE := $(LOCAL_DIR)
+
+PLATFORM := zynq
+
+# set the system base to sram
+ZYNQ_USE_SRAM := 1
+
+GLOBAL_INCLUDES += \
+	$(LOCAL_DIR)/include
+
+GLOBAL_DEFINES += \
+
+MODULE_SRCS += \
+	$(LOCAL_DIR)/target.c \
+	$(LOCAL_DIR)/init.c
+
+include make/module.mk
diff --git a/target/zybo/target.c b/target/zybo/target.c
new file mode 100644
index 00000000..78050f6b
--- /dev/null
+++ b/target/zybo/target.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2014 Travis Geiselbrecht
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+extern int ps7_init(void);
+
+void target_early_init(void)
+{
+    ps7_init();
+}
+
+void target_init(void)
+{
+}
+
+