[arch][riscv] Add support for running in supervisor mode

Add support for running LK in supervisor mode or machine mode.
- Macro-ify CSR access to use correct CSR # or use SBI call as req'd
- Add support to make SBI calls
- Split CLINT and lk timer abstraction so that RISC-V timer can use SBI
  as required.
- Add support for booting other harts as primary since hart0 on U540
  does not support S-mode. A map is used to get LK cpu number from
  hartid.

target/qemu-sifive-u/include/platform/sifive.h

@@ -18,4 +18,8 @@
 #define UART0_BASE 0x10010000
 #define UART1_BASE 0x10011000
 
-#define PLIC_HART_IDX(hart)    (2 * (hart))
+#if RISCV_XMODE_OFFSET == RISCV_MACH_OFFSET
+#define PLIC_HART_IDX(hart)    (2 * (hart))
+#elif RISCV_XMODE_OFFSET == RISCV_SUPER_OFFSET
+#define PLIC_HART_IDX(hart)    ((2 * (hart)) + 1)
+#endif

target/qemu-sifive-u/rules.mk

@@ -7,7 +7,13 @@ VARIANT := sifive_u
 
 GLOBAL_DEFINES += SIFIVE_FREQ=5000000 # 5 MHz
 
+RISCV_MODE ?= machine
+
+ifeq ($(RISCV_MODE),supervisor)
+MEMBASE ?= 0x080200000
+else
 MEMBASE ?= 0x080000000
+endif
 MEMSIZE ?= 0x200000000 # 8 GiB
 
 WITH_SMP := 0

target/sifive-unleashed/include/platform/sifive.h

@@ -21,4 +21,8 @@
 #define PWM1_BASE  0x10021000
 #define GPIO_BASE  0x10060000
 
+#if RISCV_XMODE_OFFSET == RISCV_MACH_OFFSET
 #define PLIC_HART_IDX(hart)    ((hart) ? ((2 * (hart)) - 1) : 0)
+#elif RISCV_XMODE_OFFSET == RISCV_SUPER_OFFSET
+#define PLIC_HART_IDX(hart)    ((hart) ? (2 * (hart)) : ~0U)
+#endif

target/sifive-unleashed/rules.mk

@@ -5,11 +5,19 @@ PLATFORM := sifive
 VARIANT := sifive_u
 
 WITH_SMP := 1
-SMP_MAX_CPUS := 5
+BOOT_HART := 1
 
 GLOBAL_DEFINES += SIFIVE_FREQ=500000000 # 500 MHz
 
+RISCV_MODE ?= machine
+
+ifeq ($(RISCV_MODE),supervisor)
+MEMBASE ?= 0x080200000
+SMP_MAX_CPUS := 4
+else
 MEMBASE ?= 0x080000000
+SMP_MAX_CPUS := 5
+endif
 MEMSIZE ?= 0x200000000 # 8 GiB
 
 MODULE_SRCS := $(LOCAL_DIR)/target.c