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[mp] restructure the sequence of how cpus are brought up

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- Move a bit of the shared logic of secondary bootstrapping into a new
  function, lk_secondary_cpu_entry_early() which sets the current cpu
  pointer before calling the first half of the secondary LK_INIT
  routines.
- Create the per cpu idle threads on the main cpu instead of the
  secondary as they come up.
- Tweak all of the SMP capable architectures to use this new path.
- Move the top level mp routines into a separate file top/mp.c
- A bit more correctly ifdef out more SMP code.
This commit is contained in:
Travis Geiselbrecht
2025-10-08 05:00:31 +00:00
parent e47183725d
commit e4d65228b5
15 changed files with 141 additions and 85 deletions
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4
arch/arm64/arch.c
View File

@@ -55,6 +55,10 @@ void arm64_early_init_percpu(void) {
ARM64_WRITE_SYSREG(MDSCR_EL1, 0UL); // disable debug
// clear the tpidr registers
ARM64_WRITE_SYSREG(TPIDR_EL0, 0UL);
ARM64_WRITE_SYSREG(TPIDRRO_EL0, 0UL);
// TODO: read feature bits on cpu 0
// TODO: enable cycle counter if present

13
arch/arm64/fpu.c
View File

@@ -27,8 +27,7 @@ static void arm64_fpu_load_state(struct thread *t) {
fpstate->current_cpu = cpu;
current_fpstate[cpu] = fpstate;
STATIC_ASSERT(sizeof(fpstate->regs) == 16 * 32);
STATIC_ASSERT(sizeof(fpstate->regs) == (size_t)16 * 32);
__asm__ volatile(
".arch_extension fp\n"
"ldp q0, q1, [%0, #(0 * 32)]\n"
@@ -49,8 +48,8 @@ static void arm64_fpu_load_state(struct thread *t) {
"ldp q30, q31, [%0, #(15 * 32)]\n"
"msr fpcr, %1\n"
"msr fpsr, %2\n"
".arch_extension nofp\n"
:: "r"(fpstate), "r"((uint64_t)fpstate->fpcr), "r"((uint64_t)fpstate->fpsr));
".arch_extension nofp\n" ::"r"(fpstate),
"r"((uint64_t)fpstate->fpcr), "r"((uint64_t)fpstate->fpsr));
}
void arm64_fpu_save_state(struct thread *t) {
@@ -86,13 +85,13 @@ void arm64_fpu_save_state(struct thread *t) {
}
void arm64_fpu_exception(struct arm64_iframe_long *iframe) {
uint32_t cpacr = ARM64_READ_SYSREG(cpacr_el1);
uint64_t cpacr = ARM64_READ_SYSREG(cpacr_el1);
if (((cpacr >> 20) & 3) != 3) {
cpacr |= 3 << 20;
ARM64_WRITE_SYSREG(cpacr_el1, cpacr);
thread_t *t = get_current_thread();
if (likely(t))
if (likely(t)) {
arm64_fpu_load_state(t);
return;
}
}
}

8
arch/arm64/mp.c
View File

@@ -16,6 +16,7 @@
#include <lk/main.h>
#include <lk/trace.h>
#include <platform/interrupts.h>
#include <inttypes.h>
#include <stdlib.h>
#include <string.h>
@@ -130,13 +131,14 @@ void arm64_secondary_entry(ulong asm_cpu_num) {
arm64_early_init_percpu();
/* run early secondary cpu init routines up to the threading level */
lk_init_level(LK_INIT_FLAG_SECONDARY_CPUS, LK_INIT_LEVEL_EARLIEST, LK_INIT_LEVEL_THREADING - 1);
// Get us into thread context and run the initial secondary cpu init routines
lk_secondary_cpu_entry_early();
arm64_mp_init_percpu();
LTRACEF("cpu num %d\n", cpu);
dprintf(INFO, "ARM64: secondary cpu %u started, mpidr %#" PRIx64 "\n", arch_curr_cpu_num(), ARM64_READ_SYSREG(mpidr_el1));
// Finish secondary cpu initialization and enter the scheduler
lk_secondary_cpu_entry();
}
#endif // WITH_SMP