lby/lk
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

[zynq] Remove generated init for Zybo, add platform init routines

Browse Source
This commit is contained in:
Chris Anderson
2014-08-14 12:37:30 -07:00
parent e214cda917
commit e060c035d1
8 changed files with 332 additions and 645 deletions
Download Patch File Download Diff File Expand all files Collapse all files

37
platform/zynq/include/platform/zynq.h
View File

@@ -28,6 +28,12 @@
#include <bits.h>
#endif
#ifdef ZYNQ_CLG225
#define ZYNQ_MIO_CNT 32
#else
#define ZYNQ_MIO_CNT 54
#endif
/* memory addresses */
/* assumes sram is mapped at 0 the first MB of sdram is covered by it */
#define SDRAM_BASE (0x00100000)
@@ -131,6 +137,37 @@
#ifndef ASSEMBLY
typedef struct {
uint32_t lock_cnt;
uint32_t cp;
uint32_t res;
uint32_t fdiv;
} zynq_pll_cfg_t;
typedef struct {
uint32_t arm_clk;
uint32_t ddr_clk;
uint32_t dci_clk;
uint32_t gem0_clk;
uint32_t gem0_rclk;
uint32_t lqspi_clk;
uint32_t sdio_clk;
uint32_t uart_clk;
uint32_t pcap_clk;
uint32_t fpga0_clk;
uint32_t fpga1_clk;
uint32_t fpga2_clk;
uint32_t fpga3_clk;
uint32_t aper_clk;
uint32_t clk_621_true;
} zynq_clk_cfg_t;
typedef struct {
zynq_pll_cfg_t arm;
zynq_pll_cfg_t ddr;
zynq_pll_cfg_t io;
} zynq_pll_cfg_tree_t;
/* SLCR registers */
struct slcr_regs {
uint32_t SCL; // Secure Configuration Lock

160
platform/zynq/platform.c
View File

@@ -37,6 +37,155 @@
/* target can specify this as the initial jam table to set up the soc */
__WEAK void ps7_init(void) { }
/* These should be defined in the target somewhere */
extern const uint32_t zynq_mio_cfg[ZYNQ_MIO_CNT];
extern const long zynq_ddr_cfg[];
extern const uint32_t zynq_ddr_cfg_cnt;
extern const zynq_pll_cfg_tree_t zynq_pll_cfg;
extern const zynq_clk_cfg_t zynq_clk_cfg;
static inline int reg_poll(uint32_t addr,uint32_t mask)
{
uint32_t iters = UINT_MAX;
while (iters-- && !(*REG32(addr) & mask)) ;
if (iters) {
return 0;
}
return -1;
}
/* For each PLL we need to configure the cp / res / lock_cnt and then place the PLL in bypass
* before doing a reset to switch to the new values. Then bypass is removed to switch back to using
* the PLL once its locked.
*/
int zynq_pll_init(void) {
const zynq_pll_cfg_tree_t *cfg = &zynq_pll_cfg;
zynq_slcr_unlock();
SLCR_REG(ARM_PLL_CFG) = PLL_CFG_LOCK_CNT(cfg->arm.lock_cnt) | PLL_CFG_PLL_CP(cfg->arm.cp) |
PLL_CFG_PLL_RES(cfg->arm.res);
SLCR_REG(ARM_PLL_CTRL) = PLL_FDIV(cfg->arm.fdiv) | PLL_BYPASS_FORCE | PLL_RESET;
SLCR_REG(ARM_PLL_CTRL) &= ~PLL_RESET;
if (reg_poll((uintptr_t)&SLCR->PLL_STATUS, PLL_STATUS_ARM_PLL_LOCK) == -1) {
return -1;
}
SLCR_REG(ARM_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
SLCR_REG(ARM_CLK_CTRL) = zynq_clk_cfg.arm_clk;
SLCR_REG(DDR_PLL_CFG) = PLL_CFG_LOCK_CNT(cfg->ddr.lock_cnt) | PLL_CFG_PLL_CP(cfg->ddr.cp) |
PLL_CFG_PLL_RES(cfg->ddr.res);
SLCR_REG(DDR_PLL_CTRL) = PLL_FDIV(cfg->ddr.fdiv) | PLL_BYPASS_FORCE | PLL_RESET;
SLCR_REG(DDR_PLL_CTRL) &= ~PLL_RESET;
if (reg_poll((uintptr_t)&SLCR->PLL_STATUS, PLL_STATUS_DDR_PLL_LOCK) == -1) {
return -1;
}
SLCR_REG(DDR_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
SLCR_REG(DDR_CLK_CTRL) = zynq_clk_cfg.ddr_clk;
SLCR_REG(IO_PLL_CFG) = PLL_CFG_LOCK_CNT(cfg->io.lock_cnt) | PLL_CFG_PLL_CP(cfg->io.cp) |
PLL_CFG_PLL_RES(cfg->io.res);
SLCR_REG(IO_PLL_CTRL) = PLL_FDIV(cfg->io.fdiv) | PLL_BYPASS_FORCE | PLL_RESET;
SLCR_REG(IO_PLL_CTRL) &= ~PLL_RESET;
if (reg_poll((uintptr_t)&SLCR->PLL_STATUS, PLL_STATUS_IO_PLL_LOCK) == -1) {
return -1;
}
SLCR_REG(IO_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
zynq_slcr_lock();
return 0;
}
/* TODO: This still contains some potentially Zybo specific logic and should be checked
* when switching to other Zynq boards
*/
int zynq_mio_init(void)
{
zynq_slcr_unlock();
SLCR_REG(GPIOB_CTRL) = GPIOB_CTRL_VREF_EN;
SLCR_REG(DDRIOB_ADDR0) = DDRIOB_OUTPUT_EN(0x3);
SLCR_REG(DDRIOB_ADDR1) = DDRIOB_OUTPUT_EN(0x3);
SLCR_REG(DDRIOB_DATA0) = DDRIOB_INP_TYPE(1) | DDRIOB_TERM_EN |
DDRIOB_DCI_TYPE(0x3) | DDRIOB_OUTPUT_EN(0x3);
SLCR_REG(DDRIOB_DATA1) = DDRIOB_INP_TYPE(1) | DDRIOB_TERM_EN |
DDRIOB_DCI_TYPE(0x3) | DDRIOB_OUTPUT_EN(0x3);
SLCR_REG(DDRIOB_DIFF0) = DDRIOB_INP_TYPE(2) | DDRIOB_TERM_EN |
DDRIOB_DCI_TYPE(0x3) | DDRIOB_OUTPUT_EN(0x3);
SLCR_REG(DDRIOB_DIFF1) = DDRIOB_INP_TYPE(2) | DDRIOB_TERM_EN |
DDRIOB_DCI_TYPE(0x3) | DDRIOB_OUTPUT_EN(0x3);
SLCR_REG(DDRIOB_CLOCK) = DDRIOB_OUTPUT_EN(0x3);
/* These register fields are not documented in the TRM. These
* values represent the defaults generated via the Zynq tools
*/
SLCR_REG(DDRIOB_DRIVE_SLEW_ADDR) = 0x0018C61CU;
SLCR_REG(DDRIOB_DRIVE_SLEW_DATA) = 0x00F9861CU;
SLCR_REG(DDRIOB_DRIVE_SLEW_DIFF) = 0x00F9861CU;
SLCR_REG(DDRIOB_DRIVE_SLEW_CLOCK) = 0x00F9861CU;
SLCR_REG(DDRIOB_DDR_CTRL) = 0x00000E60U;
SLCR_REG(DDRIOB_DCI_CTRL) = 0x00000001U;
SLCR_REG(DDRIOB_DCI_CTRL) |= 0x00000020U;
SLCR_REG(DDRIOB_DCI_CTRL) |= 0x00000823U;
for (size_t pin = 0; pin < countof(zynq_mio_cfg); pin++) {
if (zynq_mio_cfg[pin] != 0) {
SLCR_REG(MIO_PIN_00 + (pin * sizeof(uint32_t))) = zynq_mio_cfg[pin];
}
}
SLCR_REG(SD0_WP_CD_SEL) = SDIO0_WP_SEL(0x37) | SDIO0_CD_SEL(0x2F);
zynq_slcr_lock();
return 0;
}
void zynq_clk_init(void)
{
zynq_slcr_unlock();
SLCR_REG(DCI_CLK_CTRL) = zynq_clk_cfg.dci_clk;
SLCR_REG(GEM0_CLK_CTRL) = zynq_clk_cfg.gem0_clk;
SLCR_REG(GEM0_RCLK_CTRL) = zynq_clk_cfg.gem0_rclk;
SLCR_REG(LQSPI_CLK_CTRL) = zynq_clk_cfg.lqspi_clk;
SLCR_REG(SDIO_CLK_CTRL) = zynq_clk_cfg.sdio_clk;
SLCR_REG(UART_CLK_CTRL) = zynq_clk_cfg.uart_clk;
SLCR_REG(PCAP_CLK_CTRL) = zynq_clk_cfg.pcap_clk;
SLCR_REG(FPGA0_CLK_CTRL) = zynq_clk_cfg.fpga0_clk;
SLCR_REG(FPGA1_CLK_CTRL) = zynq_clk_cfg.fpga1_clk;
SLCR_REG(FPGA2_CLK_CTRL) = zynq_clk_cfg.fpga2_clk;
SLCR_REG(FPGA3_CLK_CTRL) = zynq_clk_cfg.fpga3_clk;
SLCR_REG(APER_CLK_CTRL) = zynq_clk_cfg.aper_clk;
SLCR_REG(CLK_621_TRUE) = zynq_clk_cfg.clk_621_true;
zynq_slcr_lock();
}
void zynq_ddr_init(void)
{
/* Write addresss / value pairs from target table */
for (size_t i = 0; i < zynq_ddr_cfg_cnt; i += 2) {
*REG32(zynq_ddr_cfg[i]) = zynq_ddr_cfg[i+1];
}
/* Wait for DCI done */
reg_poll((uintptr_t)&SLCR->DDRIOB_DCI_STATUS, 0x2000);
/* Bring ddr out of reset and wait until self refresh */
*REG32(0XF8006000) = 0x00000081U;
reg_poll(0xf8006054, 0x00000007);
/* Switch timer to 64k */
*REG32(0XF8007000) = *REG32(0xF8007000) & ~0x20000000U;
}
STATIC_ASSERT(IS_ALIGNED(SDRAM_BASE, MB));
STATIC_ASSERT(IS_ALIGNED(SDRAM_SIZE, MB));
@@ -130,9 +279,16 @@ void platform_init_mmu_mappings(void)
void platform_early_init(void)
{
ps7_init();
zynq_mio_init();
zynq_pll_init();
zynq_clk_init();
zynq_ddr_init();
/* zynq manual says this is mandatory */
/* Enable all level shifters */
SLCR_REG(LVL_SHFTR_EN) = 0xF;
/* FPGA SW reset (not documented, but mandatory) */
SLCR_REG(FPGA_RST_CTRL) = 0x0;
/* zynq manual says this is mandatory for cache init */
*REG32(SLCR_BASE + 0xa1c) = 0x020202;
/* early initialize the uart so we can printf */

10
platform/zynq/uart.c
View File

@@ -91,6 +91,10 @@ void uart_init(void)
void uart_init_early(void)
{
/**REG32(0XE0001034) = 0x00000006U; // uart1
*REG32(0XE0001018) = 0x0000003EU; // uart1
*REG32(0XE0001000) = 0x00000017U; // uart1
*REG32(0XE0001004) = 0x00000020U; // uart1<]*/
for (uint i = 0; i < NUM_UARTS; i++) {
uintptr_t base = uart_to_ptr(i);
@@ -107,6 +111,12 @@ void uart_init_early(void)
UART_REG(base, UART_CR) = (1<<4); // ~txdis, txen
}
/* Configuration for the serial console */
UART_REG(UART1_BASE, UART_BAUD_DIV) = 0x00000006;
UART_REG(UART1_BASE, UART_BAUDGEN) = 0x0000003E;
UART_REG(UART1_BASE, UART_CR) = 0x00000017;
UART_REG(UART1_BASE, UART_MR) = 0x00000020;
}
int uart_putc(int port, char c)

2
project/zybo-test.mk
View File

@@ -1,4 +1,4 @@
# top level project rules for the armemu-test project
# top level project rules for the zybo-test project
#
LOCAL_DIR := $(GET_LOCAL_DIR)

2
project/zybo.mk
View File

@@ -1,4 +1,4 @@
# top level project rules for the armemu-test project
# top level project rules for the zybo project
#
LOCAL_DIR := $(GET_LOCAL_DIR)

639
target/zybo/init.c
View File

@@ -1,639 +0,0 @@
#include <platform/zynq.h>
/*
* This file is automatically generated
*/
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Freq of all peripherals */
#define APU_FREQ 650000000
#define DDR_FREQ 525000000
#define DCI_FREQ 10159000
#define QSPI_FREQ 200000000
#define SMC_FREQ 100000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 125000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
#define UART_FREQ 50000000
#define SPI_FREQ 166666666
#define I2C_FREQ 108333336
#define WDT_FREQ 133333333
#define TTC_FREQ 50000000
#define CAN_FREQ 100000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 100000000
#define FPGA1_FREQ 175000000
#define FPGA2_FREQ 12288000
#define FPGA3_FREQ 100000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
static void perf_start_clock(void);
static void perf_disable_clock(void);
static void perf_reset_clock(void);
static void perf_reset_and_start_timer(void);
static unsigned int get_number_of_cycles_for_delay(unsigned int delay);
static inline int pll_poll(uint32_t mask)
{
uint32_t iters = UINT_MAX;
while (iters-- && !(SLCR_REG(PLL_STATUS) & mask)) ;
if (iters) {
return 0;
}
return -1;
}
int zynq_pll_init(void) {
zynq_slcr_unlock();
/* ARM PLL & Clock config
* 375 cycles needed for pll
* 26 divisor on pll
* enable all ARM clocks
* 2 divisor on ARM clocks
* ARM clock source is ARM PLL
*/
SLCR_REG(ARM_PLL_CFG) = PLL_CFG_LOCK_CNT(375) | PLL_CFG_PLL_CP(2) | PLL_CFG_PLL_RES(12);
SLCR_REG(ARM_PLL_CTRL) = PLL_FDIV(26) | PLL_BYPASS_FORCE | PLL_RESET;
SLCR_REG(ARM_PLL_CTRL) &= ~PLL_RESET;
if (pll_poll(PLL_STATUS_ARM_PLL_LOCK) == -1) {
return -1;
}
SLCR_REG(ARM_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
SLCR_REG(ARM_CLK_CTRL) = ARM_CLK_CTRL_DIVISOR(2) | ARM_CLK_CTRL_CPU_6OR4XCLKACT |
ARM_CLK_CTRL_CPU_3OR2XCLKACT | ARM_CLK_CTRL_CPU_2XCLKACT |
ARM_CLK_CTRL_CPU_1XCLKACT |ARM_CLK_CTRL_PERI_CLKACT;
#if ZYNQ_SDRAM_INIT
/* DDR PLL & Clock config
* 475 cycles needed
* 21 divisor on PLL
* enable all DDR clocks
* 2 divisor for 3XCLK, 3 divisor for 2XCLK
*/
SLCR_REG(DDR_PLL_CFG) = PLL_CFG_LOCK_CNT(475) | PLL_CFG_PLL_CP(2) | PLL_CFG_PLL_RES(12);
SLCR_REG(DDR_PLL_CTRL) = PLL_FDIV(26) | PLL_BYPASS_FORCE | PLL_RESET;
SLCR_REG(DDR_PLL_CTRL) &= ~PLL_RESET;
if (pll_poll(PLL_STATUS_DDR_PLL_LOCK) == -1) {
return -1;
}
SLCR_REG(DDR_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
SLCR_REG(DDR_CLK_CTRL) = DDR_CLK_CTRL_DDR_3XCLKACT | DDR_CLK_CTRL_DDR_2XCLKACT |
DDR_CLK_CTRL_DDR_3XCLK_DIV(2) | DDR_CLK_CTRL_DDR_2XCLK_DIV(3);
#endif
/* IO PLL config
* 500 cycles needed for pll
* 20 divisor
*/
SLCR_REG(IO_PLL_CFG) = PLL_CFG_LOCK_CNT(500) | PLL_CFG_PLL_CP(2) | PLL_CFG_PLL_RES(12);
SLCR_REG(IO_PLL_CTRL) = PLL_FDIV(20) | PLL_BYPASS_FORCE | PLL_RESET;
SLCR_REG(IO_PLL_CTRL) &= ~PLL_RESET;
if (pll_poll(PLL_STATUS_IO_PLL_LOCK) == -1) {
return -1;
}
SLCR_REG(IO_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
zynq_slcr_lock();
return 0;
}
int zynq_clk_init(void)
{
zynq_slcr_unlock();
SLCR_REG(DCI_CLK_CTRL) = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR1(52) | CLK_CTRL_DIVISOR2(2);
SLCR_REG(GEM0_RCLK_CTRL) = CLK_CTRL_CLKACT1;
SLCR_REG(GEM0_CLK_CTRL) = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR1(8) | CLK_CTRL_DIVISOR2(1);
SLCR_REG(LQSPI_CLK_CTRL) = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR1(5);
SLCR_REG(SDIO_CLK_CTRL) = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR1(20);
SLCR_REG(UART_CLK_CTRL) = CLK_CTRL_CLKACT2 | CLK_CTRL_DIVISOR1(20);
SLCR_REG(PCAP_CLK_CTRL) = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR1(5);
SLCR_REG(FPGA0_CLK_CTRL) = CLK_CTRL_DIVISOR1(10) | CLK_CTRL_DIVISOR2(1);
SLCR_REG(FPGA1_CLK_CTRL) = CLK_CTRL_SRCSEL(3) | CLK_CTRL_DIVISOR1(6) | CLK_CTRL_DIVISOR2(1);
SLCR_REG(FPGA2_CLK_CTRL) = CLK_CTRL_SRCSEL(2) | CLK_CTRL_DIVISOR1(53) | CLK_CTRL_DIVISOR2(2);
SLCR_REG(FPGA3_CLK_CTRL) = CLK_CTRL_DIVISOR2(1);
SLCR_REG(CLK_621_TRUE) = CLK_621_ENABLE;
SLCR_REG(APER_CLK_CTRL) = DMA_CPU_CLK_EN | USB0_CPU_CLK_EN | USB1_CPU_CLK_EN |
GEM0_CPU_CLK_EN | SDI0_CPU_CLK_EN | I2C0_CPU_CLK_EN |
I2C1_CPU_CLK_EN | UART1_CPU_CLK_EN | GPIO_CPU_CLK_EN |
LQSPI_CPU_CLK_EN | SMC_CPU_CLK_EN;
zynq_slcr_lock();
return 0;
}
int zynq_mio_init(void)
{
zynq_slcr_unlock();
SLCR_REG(GPIOB_CTRL) = GPIOB_CTRL_VREF_EN;
#if ZYNQ_SDRAM_INIT
SLCR_REG(DDRIOB_ADDR0) = DDRIOB_OUTPUT_EN(0x3);
SLCR_REG(DDRIOB_ADDR1) = DDRIOB_OUTPUT_EN(0x3);
SLCR_REG(DDRIOB_DATA0) = DDRIOB_INP_TYPE(1) | DDRIOB_TERM_EN |
DDRIOB_DCI_TYPE(0x3) | DDRIOB_OUTPUT_EN(0x3);
SLCR_REG(DDRIOB_DATA1) = DDRIOB_INP_TYPE(1) | DDRIOB_TERM_EN |
DDRIOB_DCI_TYPE(0x3) | DDRIOB_OUTPUT_EN(0x3);
SLCR_REG(DDRIOB_DIFF0) = DDRIOB_INP_TYPE(2) | DDRIOB_TERM_EN |
DDRIOB_DCI_TYPE(0x3) | DDRIOB_OUTPUT_EN(0x3);
SLCR_REG(DDRIOB_DIFF1) = DDRIOB_INP_TYPE(2) | DDRIOB_TERM_EN |
DDRIOB_DCI_TYPE(0x3) | DDRIOB_OUTPUT_EN(0x3);
SLCR_REG(DDRIOB_CLOCK) = DDRIOB_OUTPUT_EN(0x3);
/* These register fields are not documented in the TRM. These
* values represent the defaults generated via the Zynq tools
*/
SLCR_REG(DDRIOB_DRIVE_SLEW_ADDR) = 0x0018C61CU;
SLCR_REG(DDRIOB_DRIVE_SLEW_DATA) = 0x00F9861CU;
SLCR_REG(DDRIOB_DRIVE_SLEW_DIFF) = 0x00F9861CU;
SLCR_REG(DDRIOB_DRIVE_SLEW_CLOCK) = 0x00F9861CU;
SLCR_REG(DDRIOB_DDR_CTRL) = 0x00000E60U;
SLCR_REG(DDRIOB_DCI_CTRL) = 0x00000001U;
SLCR_REG(DDRIOB_DCI_CTRL) |= 0x00000020U;
SLCR_REG(DDRIOB_DCI_CTRL) |= 0x00000823U;
#endif
/* mio pin config */
SLCR_REG(MIO_PIN_01) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33;
SLCR_REG(MIO_PIN_02) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33;
SLCR_REG(MIO_PIN_03) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33;
SLCR_REG(MIO_PIN_04) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33;
SLCR_REG(MIO_PIN_05) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33;
SLCR_REG(MIO_PIN_06) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33;
SLCR_REG(MIO_PIN_08) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33;
SLCR_REG(MIO_PIN_16) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_DISABLE_RCVR;
SLCR_REG(MIO_PIN_17) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_DISABLE_RCVR;
SLCR_REG(MIO_PIN_18) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_DISABLE_RCVR;
SLCR_REG(MIO_PIN_19) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_DISABLE_RCVR;
SLCR_REG(MIO_PIN_20) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_DISABLE_RCVR;
SLCR_REG(MIO_PIN_21) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_DISABLE_RCVR;
SLCR_REG(MIO_PIN_22) = MIO_TRI_ENABLE | MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL;
SLCR_REG(MIO_PIN_23) = MIO_TRI_ENABLE | MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL;
SLCR_REG(MIO_PIN_24) = MIO_TRI_ENABLE | MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL;
SLCR_REG(MIO_PIN_25) = MIO_TRI_ENABLE | MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL;
SLCR_REG(MIO_PIN_26) = MIO_TRI_ENABLE | MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL;
SLCR_REG(MIO_PIN_27) = MIO_TRI_ENABLE | MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL;
SLCR_REG(MIO_PIN_28) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_29) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18 | MIO_TRI_ENABLE;
SLCR_REG(MIO_PIN_30) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_31) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18 | MIO_TRI_ENABLE;
SLCR_REG(MIO_PIN_32) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_33) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_34) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_35) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_36) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18 | MIO_TRI_ENABLE;
SLCR_REG(MIO_PIN_37) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_38) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_39) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_40) = MIO_L3_SEL(0x4) | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_41) = MIO_L3_SEL(0x4) | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_42) = MIO_L3_SEL(0x4) | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_43) = MIO_L3_SEL(0x4) | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_44) = MIO_L3_SEL(0x4) | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_45) = MIO_L3_SEL(0x4) | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_47) = MIO_TRI_ENABLE | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_48) = MIO_L3_SEL(0x7) | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_49) = MIO_TRI_ENABLE | MIO_L3_SEL(0x7) | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_52) = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_53) = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(SD0_WP_CD_SEL) = SDIO0_WP_SEL(0x37) | SDIO0_CD_SEL(0x2F);
zynq_slcr_lock();
return 0;
}
static const unsigned long ps7_pll_init_data_3_0[] = {
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001772C0U),
EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001A000U),
EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
EMIT_MASKPOLL(0XF800010C, 0x00000001U),
EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001DB2C0U),
EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00015000U),
EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
EMIT_MASKPOLL(0XF800010C, 0x00000002U),
EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001F42C0U),
EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00014000U),
EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
EMIT_MASKPOLL(0XF800010C, 0x00000004U),
EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
EMIT_EXIT(),
};
static const unsigned long ps7_clock_init_data_3_0[] = {
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203401U),
EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100630U),
EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00203520U),
EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100A00U),
EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
EMIT_EXIT(),
};
static const unsigned long ps7_ddr_init_data_3_0[] = {
EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x0000107FU),
EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004151AU),
EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E354D2U),
EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011014U),
EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0670C845U),
EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023C00U),
EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00022800U),
EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00022C00U),
EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00024800U),
EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU),
EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU),
EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000075U),
EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E4U),
EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000DFU),
EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E0U),
EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E7U),
EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU),
EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU),
EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B5U),
EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A6U),
EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
EMIT_MASKPOLL(0XF8006054, 0x00000007U),
EMIT_EXIT(),
};
static const unsigned long ps7_mio_init_data_3_0[] = {
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U),
EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E60U),
EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U),
EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002902U),
EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002902U),
EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002902U),
EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002902U),
EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002902U),
EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002902U),
EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000903U),
EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000903U),
EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000903U),
EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000903U),
EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000903U),
EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000903U),
EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
EMIT_EXIT(),
};
static const unsigned long ps7_peripherals_init_data_3_0[] = {
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
EMIT_MASKDELAY(0XF8F00200, 1),
EMIT_MASKDELAY(0XF8F00200, 1),
EMIT_MASKDELAY(0XF8F00200, 1),
EMIT_EXIT(),
};
static const unsigned long ps7_post_config_3_0[] = {
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
EMIT_EXIT(),
};
#define PS7_MASK_POLL_TIME 100000000
static void mask_write(unsigned long add, unsigned long mask, unsigned long val)
{
unsigned long *addr = (unsigned long*) add;
*addr = (val & mask)|(*addr & ~mask);
}
static int mask_poll(unsigned long add, unsigned long mask)
{
unsigned long *addr = (unsigned long*) add;
int i = 0;
while (!(*addr & mask)) {
if (i == PS7_MASK_POLL_TIME) {
return -1;
}
i++;
}
return 1;
}
static unsigned long mask_read(unsigned long add, unsigned long mask)
{
unsigned long *addr = (unsigned long*) add;
unsigned long val = (*addr & mask);
return val;
}
static int ps7_config(const unsigned long *ps7_config_init)
{
const unsigned long *ptr = ps7_config_init;
int finish = -1;
while ( finish < 0 ) {
volatile unsigned long *addr;
unsigned long val;
unsigned long mask;
int numargs = ptr[0] & 0xF;
unsigned long opcode = ptr[0] >> 4;
unsigned long args[16];
for (int j = 0 ; j < numargs ; j++)
args[j] = ptr[j+1];
ptr += numargs + 1;
switch ( opcode ) {
case OPCODE_EXIT:
finish = PS7_INIT_SUCCESS;
break;
case OPCODE_CLEAR:
addr = (unsigned long*) args[0];
*addr = 0;
break;
case OPCODE_WRITE:
addr = (unsigned long*) args[0];
val = args[1];
*addr = val;
break;
case OPCODE_MASKWRITE:
addr = (unsigned long*) args[0];
mask = args[1];
val = args[2];
*addr = ( val & mask ) | ( *addr & ~mask);
break;
case OPCODE_MASKPOLL:
addr = (unsigned long*) args[0];
mask = args[1];
int i = 0;
while (!(*addr & mask)) {
if (i == PS7_MASK_POLL_TIME) {
finish = PS7_INIT_TIMEOUT;
break;
}
i++;
}
break;
case OPCODE_MASKDELAY:
addr = (unsigned long*) args[0];
mask = args[1];
unsigned int delay = get_number_of_cycles_for_delay(mask);
perf_reset_and_start_timer();
while ((*addr < delay))
;
break;
default:
finish = PS7_INIT_CORRUPT;
break;
}
}
return finish;
}
int ps7_init(void)
{
int ret;
// MIO init
ret = zynq_mio_init();
if (ret != PS7_INIT_SUCCESS) return ret;
// PLL init
ret = zynq_pll_init();
if (ret != PS7_INIT_SUCCESS) return ret;
// Clock init
ret = zynq_clk_init();
if (ret != PS7_INIT_SUCCESS) return ret;
#if ZYNQ_SDRAM_INIT
// DDR init
ret = ps7_config (ps7_ddr_init_data_3_0);
if (ret != PS7_INIT_SUCCESS) return ret;
#endif
// Peripherals init
ret = ps7_config (ps7_peripherals_init_data_3_0);
if (ret != PS7_INIT_SUCCESS) return ret;
// post config
ret = ps7_config (ps7_post_config_3_0);
if (ret != PS7_INIT_SUCCESS) return ret;
return PS7_INIT_SUCCESS;
}
/* For delay calculation using global timer */
/* start timer */
static void perf_start_clock(void)
{
*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
(1 << 3) | // Auto-increment
(0 << 8) // Pre-scale
);
}
/* stop timer and reset timer count regs */
static void perf_reset_clock(void)
{
perf_disable_clock();
*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
}
/* Compute mask for given delay in miliseconds*/
static unsigned int get_number_of_cycles_for_delay(unsigned int delay)
{
// GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
return (APU_FREQ*delay/(2*1000));
}
/* stop timer */
static void perf_disable_clock(void)
{
*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
}
static void perf_reset_and_start_timer(void)
{
perf_reset_clock();
perf_start_clock();
}

3
target/zybo/rules.mk
View File

@@ -17,7 +17,6 @@ GLOBAL_DEFINES += \
EXTERNAL_CLOCK_FREQ=50000000
MODULE_SRCS += \
$(LOCAL_DIR)/target.c \
$(LOCAL_DIR)/init.c
$(LOCAL_DIR)/target.c
include make/module.mk

124
target/zybo/target.c
View File

@@ -1,5 +1,6 @@
/*
* Copyright (c) 2014 Travis Geiselbrecht
* Copyright (c) 2014 Chris Anderson
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
@@ -21,6 +22,129 @@
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <platform/zynq.h>
zynq_pll_cfg_tree_t zynq_pll_cfg = {
.arm = {
.lock_cnt = 375,
.cp = 2,
.res = 12,
.fdiv = 26,
},
.ddr = {
.lock_cnt = 475,
.cp = 2,
.res = 12,
.fdiv = 26,
},
.io = {
.lock_cnt = 500,
.cp = 2,
.res = 12,
.fdiv = 20,
}
};
const unsigned long zynq_ddr_cfg[] = {
0XF8006000, 0x00000080U, 0XF8006004, 0x0000107FU, 0XF8006008, 0x03C0780FU,
0XF800600C, 0x02001001U, 0XF8006010, 0x00014001U, 0XF8006014, 0x0004151AU,
0XF8006018, 0x44E354D2U, 0XF800601C, 0x720238E5U, 0XF8006020, 0x270872D0U,
0XF8006024, 0x00000000U, 0XF8006028, 0x00002007U, 0XF800602C, 0x00000008U,
0XF8006030, 0x00040930U, 0XF8006034, 0x00011014U, 0XF8006038, 0x00000000U,
0XF800603C, 0x00000777U, 0XF8006040, 0xFFF00000U, 0XF8006044, 0x0FF66666U,
0XF8006048, 0x0003C000U, 0XF8006050, 0x77010800U, 0XF8006058, 0x00000000U,
0XF800605C, 0x00005003U, 0XF8006060, 0x0000003EU, 0XF8006064, 0x00020000U,
0XF8006068, 0x00284141U, 0XF800606C, 0x00001610U, 0XF80060A4, 0x10200802U,
0XF80060A8, 0x0670C845U, 0XF80060AC, 0x000001FEU, 0XF80060B0, 0x1CFFFFFFU,
0XF80060B4, 0x00000200U, 0XF80060B8, 0x00200066U, 0XF80060C4, 0x00000003U,
0XF80060C4, 0x00000000U, 0XF80060C8, 0x00000000U, 0XF80060DC, 0x00000000U,
0XF80060F0, 0x00000000U, 0XF80060F4, 0x00000008U, 0XF8006114, 0x00000000U,
0XF8006118, 0x40000001U, 0XF800611C, 0x40000001U, 0XF8006120, 0x40000001U,
0XF8006124, 0x40000001U, 0XF800612C, 0x00023C00U, 0XF8006130, 0x00022800U,
0XF8006134, 0x00022C00U, 0XF8006138, 0x00024800U, 0XF8006140, 0x00000035U,
0XF8006144, 0x00000035U, 0XF8006148, 0x00000035U, 0XF800614C, 0x00000035U,
0XF8006154, 0x00000077U, 0XF8006158, 0x0000007CU, 0XF800615C, 0x0000007CU,
0XF8006160, 0x00000075U, 0XF8006168, 0x000000E4U, 0XF800616C, 0x000000DFU,
0XF8006170, 0x000000E0U, 0XF8006174, 0x000000E7U, 0XF800617C, 0x000000B7U,
0XF8006180, 0x000000BCU, 0XF8006184, 0x000000BCU, 0XF8006188, 0x000000B5U,
0XF8006190, 0x00040080U, 0XF8006194, 0x0001FC82U, 0XF8006204, 0x00000000U,
0XF8006208, 0x000003FFU, 0XF800620C, 0x000003FFU, 0XF8006210, 0x000003FFU,
0XF8006214, 0x000003FFU, 0XF8006218, 0x000003FFU, 0XF800621C, 0x000003FFU,
0XF8006220, 0x000003FFU, 0XF8006224, 0x000003FFU, 0XF80062A8, 0x00000000U,
0XF80062AC, 0x00000000U, 0XF80062B0, 0x00005125U, 0XF80062B4, 0x000012A6U,
};
const unsigned long zynq_ddr_cfg_cnt = countof(zynq_ddr_cfg);
const uint32_t zynq_mio_cfg[ZYNQ_MIO_CNT] = {
[1] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33,
[2] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33,
[3] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33,
[4] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33,
[5] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33,
[6] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33,
[8] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33,
[16] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_DISABLE_RCVR,
[17] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_DISABLE_RCVR,
[18] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_DISABLE_RCVR,
[19] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_DISABLE_RCVR,
[20] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_DISABLE_RCVR,
[21] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_DISABLE_RCVR,
[22] = MIO_TRI_ENABLE | MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL,
[23] = MIO_TRI_ENABLE | MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL,
[24] = MIO_TRI_ENABLE | MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL,
[25] = MIO_TRI_ENABLE | MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL,
[26] = MIO_TRI_ENABLE | MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL,
[27] = MIO_TRI_ENABLE | MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL,
[28] = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18,
[29] = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18 | MIO_TRI_ENABLE,
[30] = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18,
[31] = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18 | MIO_TRI_ENABLE,
[32] = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18,
[33] = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18,
[34] = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18,
[35] = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18,
[36] = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18 | MIO_TRI_ENABLE,
[37] = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18,
[38] = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18,
[39] = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18,
[40] = MIO_L3_SEL(0x4) | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18,
[41] = MIO_L3_SEL(0x4) | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18,
[42] = MIO_L3_SEL(0x4) | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18,
[43] = MIO_L3_SEL(0x4) | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18,
[44] = MIO_L3_SEL(0x4) | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18,
[45] = MIO_L3_SEL(0x4) | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18,
[47] = MIO_TRI_ENABLE | MIO_IO_TYPE_LVCMOS18,
[48] = MIO_L3_SEL(0x7) | MIO_IO_TYPE_LVCMOS18,
[49] = MIO_TRI_ENABLE | MIO_L3_SEL(0x7) | MIO_IO_TYPE_LVCMOS18,
[52] = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18,
[53] = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18,
};
const zynq_clk_cfg_t zynq_clk_cfg = {
.arm_clk = ARM_CLK_CTRL_DIVISOR(2) | ARM_CLK_CTRL_CPU_6OR4XCLKACT |
ARM_CLK_CTRL_CPU_3OR2XCLKACT | ARM_CLK_CTRL_CPU_2XCLKACT |
ARM_CLK_CTRL_CPU_1XCLKACT |ARM_CLK_CTRL_PERI_CLKACT,
.ddr_clk = DDR_CLK_CTRL_DDR_3XCLKACT | DDR_CLK_CTRL_DDR_2XCLKACT |
DDR_CLK_CTRL_DDR_3XCLK_DIV(2) | DDR_CLK_CTRL_DDR_2XCLK_DIV(3),
.dci_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(52) | CLK_CTRL_DIVISOR1(2),
.gem0_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(8) | CLK_CTRL_DIVISOR1(1),
.gem0_rclk = CLK_CTRL_CLKACT,
.lqspi_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(5),
.sdio_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(20),
.uart_clk = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR0(20),
.pcap_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(5),
.fpga0_clk = CLK_CTRL_DIVISOR0(10) | CLK_CTRL_DIVISOR1(1),
.fpga1_clk = CLK_CTRL_SRCSEL(3) | CLK_CTRL_DIVISOR0(6) | CLK_CTRL_DIVISOR1(1),
.fpga2_clk = CLK_CTRL_SRCSEL(2) | CLK_CTRL_DIVISOR0(53) | CLK_CTRL_DIVISOR1(2),
.fpga3_clk = CLK_CTRL_DIVISOR1(1),
.aper_clk = DMA_CPU_CLK_EN | USB0_CPU_CLK_EN | USB1_CPU_CLK_EN |
GEM0_CPU_CLK_EN | SDI0_CPU_CLK_EN | I2C0_CPU_CLK_EN |
I2C1_CPU_CLK_EN | UART1_CPU_CLK_EN | GPIO_CPU_CLK_EN |
LQSPI_CPU_CLK_EN | SMC_CPU_CLK_EN,
.clk_621_true = CLK_621_ENABLE,
};
void target_early_init(void)
{
}