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[stm32f0xx] Add support for stm32f070xb

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This cleans up handling of a lot of optional components
across f0xx models.
This commit is contained in:
Todd Eisenberger
2018-04-14 19:32:40 -07:00
committed by Travis Geiselbrecht
parent e07741036d
commit e007acc4dc
9 changed files with 133 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
external/platform/stm32f0xx/CMSIS/inc/stm32f0xx.h vendored
View File

@@ -75,6 +75,9 @@
#ifdef STM32F072
#define STM32F072xB
#endif
#ifdef STM32F070
#define STM32F070xB
#endif
/* Uncomment the line below according to the target STM32 device used in your
application

4
platform/stm32f0xx/can.c
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@@ -1,3 +1,5 @@
#if defined(STM32F072xB)
#include <platform/can.h>
#include <assert.h>
@@ -208,3 +210,5 @@ ssize_t can_recv(can_msg_t *msg, bool block)
return bytes_read > 0 ? msg->dlc : -EWOULDBLOCK;
}
#endif // STM32F072xB

30
platform/stm32f0xx/gpio.c
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@@ -60,18 +60,30 @@ static stm32_gpio_t *stm32_gpio_port_to_pointer(unsigned int port)
{
switch (port) {
default:
#ifdef GPIOA
case GPIO_PORT_A:
return GPIOA;
#endif
#ifdef GPIOB
case GPIO_PORT_B:
return GPIOB;
#endif
#ifdef GPIOC
case GPIO_PORT_C:
return GPIOC;
#endif
#ifdef GPIOD
case GPIO_PORT_D:
return GPIOD;
#endif
#ifdef GPIOE
case GPIO_PORT_E:
return GPIOE;
#endif
#ifdef GPIOF
case GPIO_PORT_F:
return GPIOF;
#endif
}
}
@@ -81,30 +93,36 @@ static void stm32_gpio_enable_port(unsigned int port)
switch (port) {
default:
#ifdef GPIOA
case GPIO_PORT_A:
stm32_rcc_set_enable(STM32_RCC_CLK_IOPA, true);
break;
#endif
#ifdef GPIOB
case GPIO_PORT_B:
stm32_rcc_set_enable(STM32_RCC_CLK_IOPB, true);
break;
#endif
#ifdef GPIOC
case GPIO_PORT_C:
stm32_rcc_set_enable(STM32_RCC_CLK_IOPC, true);
break;
#endif
#ifdef GPIOD
case GPIO_PORT_D:
stm32_rcc_set_enable(STM32_RCC_CLK_IOPD, true);
break;
#endif
#ifdef GPIOE
case GPIO_PORT_E:
stm32_rcc_set_enable(STM32_RCC_CLK_IOPE, true);
break;
#endif
#ifdef GPIOF
case GPIO_PORT_F:
stm32_rcc_set_enable(STM32_RCC_CLK_IOPF, true);
break;
#endif
}
}

12
platform/stm32f0xx/include/platform/exti.h
View File

@@ -5,12 +5,24 @@
#include <stm32f0xx.h>
typedef enum {
#ifdef SYSCFG_EXTICR1_EXTI0_PA
EXT_INTERRUPT_PORT_A = SYSCFG_EXTICR1_EXTI0_PA,
#endif
#ifdef SYSCFG_EXTICR1_EXTI0_PB
EXT_INTERRUPT_PORT_B = SYSCFG_EXTICR1_EXTI0_PB,
#endif
#ifdef SYSCFG_EXTICR1_EXTI0_PC
EXT_INTERRUPT_PORT_C = SYSCFG_EXTICR1_EXTI0_PC,
#endif
#ifdef SYSCFG_EXTICR1_EXTI0_PD
EXT_INTERRUPT_PORT_D = SYSCFG_EXTICR1_EXTI0_PD,
#endif
#ifdef SYSCFG_EXTICR1_EXTI0_PE
EXT_INTERRUPT_PORT_E = SYSCFG_EXTICR1_EXTI0_PE,
#endif
#ifdef SYSCFG_EXTICR1_EXTI0_PF
EXT_INTERRUPT_PORT_F = SYSCFG_EXTICR1_EXTI0_PF,
#endif
} stm32_ext_interrupt_port_t;
void stm32_setup_ext_interrupt(int interrupt, stm32_ext_interrupt_port_t port,

14
platform/stm32f0xx/include/platform/gpio.h
View File

@@ -1,6 +1,8 @@
#ifndef __PLATFORM_STM32_GPIO_H
#define __PLATFORM_STM32_GPIO_H
#include <stm32f0xx.h>
/* helper defines for STM32 platforms */
/* flag to gpio_configure */
@@ -15,12 +17,24 @@
#define GPIO_PIN(gpio) ((gpio) & 0xff)
#define GPIO_AFNUM(gpio) (((gpio) >> 24) & 0xf)
#ifdef GPIOA
#define GPIO_PORT_A 0
#endif
#ifdef GPIOB
#define GPIO_PORT_B 1
#endif
#ifdef GPIOC
#define GPIO_PORT_C 2
#endif
#ifdef GPIOD
#define GPIO_PORT_D 3
#endif
#ifdef GPIOE
#define GPIO_PORT_E 4
#endif
#ifdef GPIOF
#define GPIO_PORT_F 5
#endif
#endif

4
platform/stm32f0xx/rules.mk
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@@ -10,6 +10,10 @@ MEMBASE := 0x20000000
ARCH := arm
ARM_CPU := cortex-m0
ifeq ($(STM32_CHIP),stm32f070_xB)
GLOBAL_DEFINES += STM32F070
MEMSIZE ?= 16384
endif
ifeq ($(STM32_CHIP),stm32f072_x8)
GLOBAL_DEFINES += \
STM32F072

18
platform/stm32f0xx/timer_capture.c
View File

@@ -52,6 +52,7 @@ typedef struct stm32_timer_config_ {
} stm32_timer_config_t;
static const stm32_timer_config_t stm32_timer_config[] = {
#ifdef TIM1
[STM32_TIM1_INDEX] = {
.regs = TIM1,
.flags = 0,
@@ -61,54 +62,71 @@ static const stm32_timer_config_t stm32_timer_config[] = {
// supported.
.irq = TIM1_CC_IRQn,
},
#endif
#ifdef TIM2
[STM32_TIM2_INDEX] = {
.regs = TIM2,
.flags = STM32_TIMER_FLAGS_32_BIT,
.clock = STM32_RCC_CLK_TIM2,
.irq = TIM2_IRQn,
},
#endif
#ifdef TIM3
[STM32_TIM3_INDEX] = {
.regs = TIM3,
.flags = 0,
.clock = STM32_RCC_CLK_TIM3,
.irq = TIM3_IRQn,
},
#endif
#ifdef TIM6
[STM32_TIM6_INDEX] = {
.regs = TIM6,
.flags = 0,
.clock = STM32_RCC_CLK_TIM6,
.irq = TIM6_IRQn,
},
#endif
#ifdef TIM7
[STM32_TIM7_INDEX] = {
.regs = TIM7,
.flags = 0,
.clock = STM32_RCC_CLK_TIM7,
.irq = TIM7_IRQn,
},
#endif
#ifdef TIM14
[STM32_TIM14_INDEX] = {
.regs = TIM14,
.flags = 0,
.clock = STM32_RCC_CLK_TIM14,
.irq = TIM14_IRQn,
},
#endif
#ifdef TIM15
[STM32_TIM15_INDEX] = {
.regs = TIM15,
.flags = 0,
.clock = STM32_RCC_CLK_TIM15,
.irq = TIM15_IRQn,
},
#endif
#ifdef TIM16
[STM32_TIM16_INDEX] = {
.regs = TIM16,
.flags = 0,
.clock = STM32_RCC_CLK_TIM16,
.irq = TIM16_IRQn,
},
#endif
#ifdef TIM17
[STM32_TIM17_INDEX] = {
.regs = TIM17,
.flags = 0,
.clock = STM32_RCC_CLK_TIM17,
.irq = TIM17_IRQn,
},
#endif
};
static stm32_timer_capture_t *stm32_timer_capture_data[STM32_NUM_TIMERS];

40
platform/stm32f0xx/uart.c
View File

@@ -57,11 +57,11 @@ cbuf_t uart3_rx_buf;
#endif
#endif
#ifdef ENABLE_UART1
#ifdef ENABLE_UART4
cbuf_t uart4_rx_buf;
#ifndef UART4_FLOWCONTROL
#define UART4_FLOWCONTROL 0x0
#endif
#ifdef ENABLE_UART2
#endif
#ifdef ENABLE_UART3
#endif
static void stm32_usart_init1_early(stm32_usart_t *usart,
@@ -104,6 +104,10 @@ static void stm32_usart_init1(stm32_usart_t *usart, int irqn, cbuf_t *rxbuf)
NVIC_EnableIRQ(irqn);
}
#if defined(ENABLE_UART3) && defined(ENABLE_UART4)
#error UART3 and 4 share an interrupt; not supported
#endif
void uart_init_early(void)
{
#ifdef ENABLE_UART1
@@ -115,6 +119,9 @@ void uart_init_early(void)
#ifdef ENABLE_UART3
stm32_rcc_set_enable(STM32_RCC_CLK_USART3, true);
#endif
#ifdef ENABLE_UART4
stm32_rcc_set_enable(STM32_RCC_CLK_USART4, true);
#endif
#ifdef ENABLE_UART1
stm32_usart_init1_early(USART1, UART1_FLOWCONTROL, USART1_IRQn);
@@ -123,7 +130,10 @@ void uart_init_early(void)
stm32_usart_init1_early(USART2, UART2_FLOWCONTROL, USART2_IRQn);
#endif
#ifdef ENABLE_UART3
stm32_usart_init1_early(USART3, UART3_FLOWCONTROL, USART3_IRQn);
stm32_usart_init1_early(USART3, UART3_FLOWCONTROL, USART3_4_IRQn);
#endif
#ifdef ENABLE_UART4
stm32_usart_init1_early(USART4, UART4_FLOWCONTROL, USART3_4_IRQn);
#endif
}
@@ -136,7 +146,10 @@ void uart_init(void)
stm32_usart_init1(USART2, USART2_IRQn, &uart2_rx_buf);
#endif
#ifdef ENABLE_UART3
stm32_usart_init1(USART3, USART3_IRQn, &uart3_rx_buf);
stm32_usart_init1(USART3, USART3_4_IRQn, &uart3_rx_buf);
#endif
#ifdef ENABLE_UART4
stm32_usart_init1(USART4, USART3_4_IRQn, &uart4_rx_buf);
#endif
}
@@ -183,6 +196,10 @@ static cbuf_t *stm32_get_rxbuf(int port)
#ifdef ENABLE_UART3
case 3:
return &uart3_rx_buf;
#endif
#ifdef ENABLE_UART4
case 4:
return &uart4_rx_buf;
#endif
default:
ASSERT(false);
@@ -211,6 +228,13 @@ void stm32_USART3_IRQ(void)
}
#endif
#ifdef ENABLE_UART4
void stm32_USART4_IRQ(void)
{
stm32_uart_rx_irq(USART4, stm32_get_rxbuf(4));
}
#endif
static void stm32_usart_putc(stm32_usart_t *usart, char c)
{
@@ -243,6 +267,10 @@ static stm32_usart_t *stm32_get_usart(int port)
#ifdef ENABLE_UART3
case 3:
return USART3;
#endif
#ifdef ENABLE_UART4
case 4:
return USART4;
#endif
default:
ASSERT(false);

20
platform/stm32f0xx/vectab.c
View File

@@ -78,28 +78,46 @@ DEFAULT_HANDLER(USB_IRQ)
/* appended to the end of the main vector table */
const void *const __SECTION(".text.boot.vectab2") vectab2[] = {
VECTAB_ENTRY(WWDG_IRQ), // Window WatchDog Interrupt
#ifdef PVD_IRQ
VECTAB_ENTRY(PVD_IRQ), // PVD through EXTI Line detect Interrupt
#endif
VECTAB_ENTRY(RTC_IRQ), // RTC through EXTI Line Interrupt
VECTAB_ENTRY(FLASH_IRQ), // FLASH Interrupt
VECTAB_ENTRY(RCC_IRQ), // RCC Interrupt
VECTAB_ENTRY(EXTI0_1_IRQ), // EXTI Line 0 and 1 Interrupts
VECTAB_ENTRY(EXTI2_3_IRQ), // EXTI Line 2 and 3 Interrupts
VECTAB_ENTRY(EXTI4_15_IRQ), // EXTI Line 4 to 15 Interrupts
#ifdef TSC_IRQ
VECTAB_ENTRY(TSC_IRQ), // Touch sense controller Interrupt
#endif
VECTAB_ENTRY(DMA1_Channel1_IRQ), // DMA1 Channel 1 Interrupt
VECTAB_ENTRY(DMA1_Channel2_3_IRQ), // DMA1 Channel 2 and Channel 3 Interrupts
VECTAB_ENTRY(DMA1_Channel4_5_6_7_IRQ), // DMA1 Channels 4-7 Interrupts
VECTAB_ENTRY(ADC1_COMP_IRQ), // ADC1, COMP1 and COMP2 Interrupts
VECTAB_ENTRY(TIM1_BRK_UP_TRG_COM_IRQ), // TIM1 Break, Update, Trigger and Commutation Interrupts
VECTAB_ENTRY(TIM1_CC_IRQ), // TIM1 Capture Compare Interrupt
#ifdef TIM2_IRQ
VECTAB_ENTRY(TIM2_IRQ), // TIM2 Interrupt
#endif
#ifdef TIM3_IRQ
VECTAB_ENTRY(TIM3_IRQ), // TIM3 Interrupt
#endif
VECTAB_ENTRY(TIM6_DAC_IRQ), // TIM6 and DAC Interrupts
#ifdef TIM7_IRQ
VECTAB_ENTRY(TIM7_IRQ), // TIM7 Interrupts
#endif
#ifdef TIM14_IRQ
VECTAB_ENTRY(TIM14_IRQ), // TIM14 Interrupt
#endif
#ifdef TIM15_IRQ
VECTAB_ENTRY(TIM15_IRQ), // TIM15 Interrupt
#endif
#ifdef TIM16_IRQ
VECTAB_ENTRY(TIM16_IRQ), // TIM16 Interrupt
#endif
#ifdef TIM17_IRQ
VECTAB_ENTRY(TIM17_IRQ), // TIM17 Interrupt
#endif
VECTAB_ENTRY(I2C1_IRQ), // I2C1 Interrupt
VECTAB_ENTRY(I2C2_IRQ), // I2C2 Interrupt
VECTAB_ENTRY(SPI1_IRQ), // SPI1 Interrupt
@@ -107,6 +125,8 @@ const void *const __SECTION(".text.boot.vectab2") vectab2[] = {
VECTAB_ENTRY(USART1_IRQ), // USART1 Interrupt
VECTAB_ENTRY(USART2_IRQ), // USART2 Interrupt
VECTAB_ENTRY(USART3_4_IRQ), // USART3 and USART4 Interrupts
#ifdef CEC_CAN_IRQ
VECTAB_ENTRY(CEC_CAN_IRQ), // CEC Interrupt
#endif
VECTAB_ENTRY(USB_IRQ), // USB Low Priority global Interrupt
};