[msm] initial qsd8k support (tested on qsd8250 surf)
This commit is contained in:
Brian Swetland
541
platform/qsd8k/arch_init.S
Normal file
541
platform/qsd8k/arch_init.S
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@@ -0,0 +1,541 @@
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/*
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* Copyright (c) 2008, QUALCOMM Incorporated.
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* Copyright (c) 2008, Google Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Google, Inc. nor the names of its contributors
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* may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* TODO:
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* - style cleanup
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* - do we need to do *all* of this at boot?
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*/
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.text
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.code 32
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#define DSB .byte 0x4f, 0xf0, 0x7f, 0xf5
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#define ISB .byte 0x6f, 0xf0, 0x7f, 0xf5
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/*
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; LVT Ring Osc counter
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; used to determine sense amp settings
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; Clobbers registers r0, r4, r5, r6, r7, r9, r10, r11
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*/
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.equ CLK_CTL_BASE, 0xA8600000
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.equ A_GLBL_CLK_ENA, 0x0000
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.equ A_PRPH_WEB_NS_REG,0x0080
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.equ A_MSM_CLK_RINGOSC,0x00D0
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.equ A_TCXO_CNT, 0x00D4
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.equ A_TCXO_CNT_DONE, 0x00D8
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.equ A_RINGOSC_CNT, 0x00DC
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.equ A_MISC_CLK_CTL, 0x0108
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.equ CLK_TEST, 0xA8600114
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.equ SPSS_CSR_BASE, 0xAC100000
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.equ A_SCRINGOSC, 0x0510
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//;; Number of TCXO cycles to count ring oscillations
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.equ TCXO_CNT_VAL, 0x100
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SET_SA:
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//; clear CLK_TEST[19] (RING_OSC_DBG_SEL) to count ring osc
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LDR r5, =CLK_TEST
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LDR r4, [r5]
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BIC r4, r4, #0x80000
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STR r4, [r5]
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//; setup memory pointers
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LDR r5, =CLK_CTL_BASE
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LDR r6, =SPSS_CSR_BASE
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//; PRPH_WEB_NS_REG = 0x00000A00 - enable root and crc
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MOV r7, #0x0A00
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STR r7,[r5,#A_PRPH_WEB_NS_REG]
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//; MISC_CLK_CTL = 0x0 to disable tcxo4cnt, ringosccnt
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MOV r0, #0
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STR r0,[r5,#A_MISC_CLK_CTL]
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DSB
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//;; MSM_CLK_RINGOSC = 0x00000A0E
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//;; the E selects Scorpion LVT RO(or DS) output,
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//;; the A enables RO CRC and CXC
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LDR r7, =0x0A0E
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STR r7,[r5,#A_MSM_CLK_RINGOSC]
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MOV r10, #0x1 //; SCRINGOSC[1:0] = 01
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MOV r11, #TCXO_CNT_VAL
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//;; initialize r9 - counts the 4 oscillators
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MOV r9,#0x0
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LDR r4,=RO_CNT
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ACQUIRE_FREQ:
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//; SCRINGOSC[1:0] is set by r10, [13:11][10:8] = 0..7
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//;MOV r7, r10
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BIC r7, r10, #0x3F00
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//;BFI r7, r9, #8, #3
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ORR r7, r7, r9, LSL #8
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//;BFI r7, r9, #11, #3
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ORR r7, r7, r9, LSL #11
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STR r7,[r6,#A_SCRINGOSC]
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STR r11,[r5,#A_TCXO_CNT]
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DSB //; Make sure the countdown value gets written before the ROs are enabled
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//; MISC_CLK_CTL = 0x3 to enable tcxo4cnt, ringosccnt
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MOV r7,#0x3
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STR r7,[r5,#A_MISC_CLK_CTL]
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//;; According to Raptor HDD, to read TCXO_CNT_DONE, use address for TCXO_CNT on pass1.
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//;; Then read RINGOSC_CNT and store to debug_mem table
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WAIT_TCXO_CNT_DONE:
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LDR r7,[r5,#A_TCXO_CNT_DONE]
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CMP r7,#0x1
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BNE WAIT_TCXO_CNT_DONE
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LDR r7,[r5,#A_RINGOSC_CNT]
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STR r7,[r4],#0x04 //; post-indexed update r4 to next empty table entry
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//; MISC_CLK_CTL = 0x0 to disable tcxo4cnt, ringosccnt
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STR r0,[r5,#A_MISC_CLK_CTL]
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DSB
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//;; move to next oscillator - r9 counts oscillators 0..7
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ADD r9,r9,#1
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CMP r9,#0x4
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BLT ACQUIRE_FREQ
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//; average the 4 counts
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LDR r4,=RO_CNT
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LDR r5, [r4], #0x4
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LDR r6, [r4], #0x4
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ADD r5, r5, r6
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LDR r6, [r4], #0x4
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ADD r5, r5, r6
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LDR r6, [r4], #0x4
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ADD r5, r5, r6
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MOV r5, r5, LSR #2
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.equ SLOW_THRESHOLD, 0x0E10
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.equ NOM_THRESHOLD, 0x123A
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//; compare average to slow part threshold
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LDR r4, =SLOW_THRESHOLD
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CMP r5, r4
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LDRLT r4, =SLOW_SA
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BLT WRITE_SA
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//; compare average to nominal part threshold
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LDR r4, =NOM_THRESHOLD
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CMP r5, r4
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LDRLT r4, =NOM_SA
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BLT WRITE_SA
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//; must be fast part
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LDR r4, =FAST_SA
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B WRITE_SA
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SLOW_SA:
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.word 0x38001C00 //; PVR0F0
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.word 0x1C000000 //; PVR2F0
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.word 0x00212102 //; L2VR3F1
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NOM_SA:
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.word 0x38001C00 //; PVR0F0
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.word 0x1C000000 //; PVR2F0
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.word 0x00212102 //; L2VR3F1
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FAST_SA:
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.word 0x38003C00 //; PVR0F0
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.word 0x1C000000 //; PVR2F0
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.word 0x00212102 //; L2VR3F1
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RO_CNT:
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.word 0x0
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.word 0x0
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.word 0x0
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.word 0x0
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WRITE_SA:
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//; write the sense amp settings
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//; PVR0F0[15:10] = I$
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LDR r5, [r4], #4
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//;WCP15_PVR0F0 r5
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MCR p15,0x0,r5,c15,c15,0
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//; PVR2F0[31:26] = D$
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LDR r5, [r4], #4
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//;WCP15_PVR2F0 r5
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MCR p15,0x2,r5,c15,c15,0
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//; L2VR3F1[23:0]
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LDR r5, [r4], #4
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//;WCP15_L2VR3F1 r5
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MCR p15,0x3,r5,c15,c15,1
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ISB
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BX lr
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.globl __cpu_early_init
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__cpu_early_init:
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//; Zero out r0 for use throughout this code. All other GPRs
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//; (r1-r3) are set throughout this code to help establish
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//; a consistent startup state for any code that follows.
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//; Users should add code at the end of this routine to establish
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//; their own stack address (r13), add translation page tables, enable
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//; the caches, etc.
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MOV r0, #0x0
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//; Write L2VR3F1 to make L2 array work properly at 998 on Raptor2
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LDR r1, =0x00212102 //; the l2 timing watch out on P2
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MCR p15, 3, r1, c15, c15, 1 //; WCP15_L2VR3F1
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DSB
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ISB
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//; write the value for Icache to run at 998 on Raptor2
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LDR r1, =0x3800E000
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MCR p15, 0, r1, c15, c15, 0 //; WCP15_PVR0F0
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ISB
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//; DCIALL to invalidate L2 cache bank (needs to be run 4 times, once per bank)
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//; This must be done early in code (prior to enabling the caches)
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MOV r1, #0x2
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MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank D ([15:14] == 2'b00)
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ORR r1, r1, #0x00004000
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MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank C ([15:14] == 2'b01)
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ADD r1, r1, #0x00004000
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MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank B ([15:14] == 2'b10)
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ADD r1, r1, #0x00004000
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MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank A ([15:14] == 2'b11)
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//; Initialize the BPCR - setup Global History Mask (GHRM) to all 1's
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//; and have all address bits (AM) participate.
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//; Different settings can be used to improve performance
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.word 0xe30011ff // MOVW r1, #0x01FF
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.word 0xe34011ff // MOVT r1, #0x01FF
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MCR p15, 7, r1, c15, c0, 2 //; WCP15_BPCR
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//; Initialize all I$ Victim Registers to 0 for startup
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MCR p15, 0, r0, c9, c1, 0 //; WCP15_ICVIC0 r0
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MCR p15, 0, r0, c9, c1, 1 //; WCP15_ICVIC1 r0
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MCR p15, 0, r0, c9, c1, 2 //; WCP15_ICVIC2 r0
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MCR p15, 0, r0, c9, c1, 3 //; WCP15_ICVIC3 r0
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MCR p15, 0, r0, c9, c1, 4 //; WCP15_ICVIC4 r0
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MCR p15, 0, r0, c9, c1, 5 //; WCP15_ICVIC5 r0
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MCR p15, 0, r0, c9, c1, 6 //; WCP15_ICVIC5 r0
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MCR p15, 0, r0, c9, c1, 7 //; WCP15_ICVIC7 r0
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//; Initialize all I$ Locked Victim Registers (Unlocked Floors) to 0
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MCR p15, 1, r0, c9, c1, 0 //; WCP15_ICFLOOR0 r0
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MCR p15, 1, r0, c9, c1, 1 //; WCP15_ICFLOOR1 r0
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MCR p15, 1, r0, c9, c1, 2 //; WCP15_ICFLOOR2 r0
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MCR p15, 1, r0, c9, c1, 3 //; WCP15_ICFLOOR3 r0
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MCR p15, 1, r0, c9, c1, 4 //; WCP15_ICFLOOR4 r0
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MCR p15, 1, r0, c9, c1, 5 //; WCP15_ICFLOOR5 r0
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MCR p15, 1, r0, c9, c1, 6 //; WCP15_ICFLOOR6 r0
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MCR p15, 1, r0, c9, c1, 7 //; WCP15_ICFLOOR7 r0
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//; Initialize all D$ Victim Registers to 0
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MCR p15, 2, r0, c9, c1, 0 //; WP15_DCVIC0 r0
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MCR p15, 2, r0, c9, c1, 1 //; WP15_DCVIC1 r0
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MCR p15, 2, r0, c9, c1, 2 //; WP15_DCVIC2 r0
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MCR p15, 2, r0, c9, c1, 3 //; WP15_DCVIC3 r0
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MCR p15, 2, r0, c9, c1, 4 //; WP15_DCVIC4 r0
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MCR p15, 2, r0, c9, c1, 5 //; WP15_DCVIC5 r0
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MCR p15, 2, r0, c9, c1, 6 //; WP15_DCVIC6 r0
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MCR p15, 2, r0, c9, c1, 7 //; WP15_DCVIC7 r0
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//; Initialize all D$ Locked VDCtim Registers (Unlocked Floors) to 0
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MCR p15, 3, r0, c9, c1, 0 //; WCP15_DCFLOOR0 r0
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MCR p15, 3, r0, c9, c1, 1 //; WCP15_DCFLOOR1 r0
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MCR p15, 3, r0, c9, c1, 2 //; WCP15_DCFLOOR2 r0
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MCR p15, 3, r0, c9, c1, 3 //; WCP15_DCFLOOR3 r0
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MCR p15, 3, r0, c9, c1, 4 //; WCP15_DCFLOOR4 r0
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MCR p15, 3, r0, c9, c1, 5 //; WCP15_DCFLOOR5 r0
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MCR p15, 3, r0, c9, c1, 6 //; WCP15_DCFLOOR6 r0
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MCR p15, 3, r0, c9, c1, 7 //; WCP15_DCFLOOR7 r0
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//; Initialize ASID to zero
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MCR p15, 0, r0, c13, c0, 1 //; WCP15_CONTEXTIDR r0
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//; ICIALL to invalidate entire I-Cache
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MCR p15, 0, r0, c7, c5, 0 //; ICIALLU
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//; DCIALL to invalidate entire D-Cache
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MCR p15, 0, r0, c9, c0, 6 //; DCIALL r0
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//; The VBAR (Vector Base Address Register) should be initialized
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//; early in your code. We are setting it to zero
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MCR p15, 0, r0, c12, c0, 0 //; WCP15_VBAR r0
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//; Ensure the MCR's above have completed their operation before continuing
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DSB
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ISB
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//;-------------------------------------------------------------------
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//; There are a number of registers that must be set prior to enabling
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//; the MMU. The DCAR is one of these registers. We are setting
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//; it to zero (no access) to easily detect improper setup in subsequent
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//; code sequences
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//;-------------------------------------------------------------------
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//; Setup DACR (Domain Access Control Register) to zero
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MCR p15, 0, r0, c3, c0, 0 //; WCP15_DACR r0
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//; Setup DCLKCR to allow normal D-Cache line fills
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MCR p15, 1, r0, c9, c0, 7 //; WCP15_DCLKCR r0
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//; Setup the TLBLKCR
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//; Victim = 6'b000000; Floor = 6'b000000;
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//; IASIDCFG = 2'b00 (State-Machine); IALLCFG = 2'b01 (Flash); BNA = 1'b0;
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MOV r1, #0x02
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MCR p15, 0, r1, c10, c1, 3 //; WCP15_TLBLKCR r1
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//;Make sure TLBLKCR is complete before continuing
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ISB
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//; Invalidate the UTLB
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MCR p15, 0, r0, c8, c7, 0 //; UTLBIALL
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//; Make sure UTLB request has been presented to macro before continuing
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ISB
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//; setup L2CR1 to some default Instruction and data prefetching values
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//; Users may want specific settings for various performance enhancements
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MCR p15, 3, r0, c15, c0, 3 //; WCP15_L2CR1 r0
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//; Enable Z bit to enable branch prediction (default is off)
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MRC p15, 0, r2, c1, c0, 0 //; RCP15_SCTLR r2
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ORR r2, r2, #0x00000800
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MCR p15, 0, r2, c1, c0, 0 //; WCP15_SCTLR r2
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mov r1, lr
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//; Make sure Link stack is initialized with branch and links to sequential addresses
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//; This aids in creating a predictable startup environment
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BL SEQ1
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SEQ1: BL SEQ2
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SEQ2: BL SEQ3
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SEQ3: BL SEQ4
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SEQ4: BL SEQ5
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SEQ5: BL SEQ6
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SEQ6: BL SEQ7
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SEQ7: BL SEQ8
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SEQ8:
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mov lr, r1
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//; REMOVE FOLLOWING THREE INSTRUCTIONS WHEN POWER COLLAPSE IS ENA
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//;Make sure the DBGOSLSR[LOCK] bit is cleared to allow access to the debug registers
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//; Writing anything but the "secret code" to the DBGOSLAR clears the DBGOSLSR[LOCK] bit
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MCR p14, 0, r0, c1, c0, 4 //; WCP14_DBGOSLAR r0
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//; Read the DBGPRSR to clear the DBGPRSR[STICKYPD]
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//; Any read to DBGPRSR clear the STICKYPD bit
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//; ISB guarantees the read completes before attempting to
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//; execute a CP14 instruction.
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MRC p14, 0, r3, c1, c5, 4 //; RCP14_DBGPRSR r3
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ISB
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//; Initialize the Watchpoint Control Registers to zero (optional)
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//;;; MCR p14, 0, r0, c0, c0, 7 ; WCP14_DBGWCR0 r0
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//;;; MCR p14, 0, r0, c0, c1, 7 ; WCP14_DBGWCR1 r0
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||||
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//;----------------------------------------------------------------------
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||||
//; Enabling Error reporting is something users may want to do at
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||||
//; some other point in time. We have chosen some default settings
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||||
//; that should be reviewed. Most of these registers come up in an
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||||
//; unpredictable state after reset.
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//;----------------------------------------------------------------------
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//;Start of error and control setting
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||||
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//; setup L2CR0 with various L2/TCM control settings
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||||
//; enable out of order bus attributes and error reporting
|
||||
//; this register comes up unpredictable after reset
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||||
.word 0xe3001f0f // MOVW r1, #0x0F0F
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.word 0xe34c1005 // MOVT r1, #0xC005
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||||
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||||
MCR p15, 3, r1, c15, c0, 1 //; WCP15_L2CR0 r1
|
||||
|
||||
//; setup L2CPUCR
|
||||
MOV r2, #0
|
||||
MCR p15, 3, r2, c15, c0, 2 //; WCP15_L2CPUCR r2
|
||||
|
||||
//; setup SPCR
|
||||
//; enable all error reporting (reset value is unpredicatble for most bits)
|
||||
MOV r3, #0x0F
|
||||
MCR p15, 0, r3, c9, c7, 0 //; WCP15_SPCR r3
|
||||
|
||||
|
||||
//; setup DMACHCRs (reset value unpredictable)
|
||||
//; control setting and enable all error reporting
|
||||
MOV r1, #0x0F
|
||||
|
||||
//; DMACHCR0 = 0000000F
|
||||
MOV r2, #0x00 //; channel 0
|
||||
MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
|
||||
MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
|
||||
|
||||
//; DMACHCR1 = 0000000F
|
||||
MOV r2, #0x01 //; channel 1
|
||||
MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
|
||||
MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
|
||||
|
||||
//; DMACHCR2 = 0000000F
|
||||
MOV r2, #0x02 //; channel 2
|
||||
MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
|
||||
MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
|
||||
|
||||
//; DMACHCR3 = 0000000F
|
||||
MOV r2, #0x03 //; channel 3
|
||||
MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
|
||||
MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
|
||||
|
||||
//; Set ACTLR (reset unpredictable)
|
||||
//; Set AVIVT control, error reporting, etc.
|
||||
MOV r3, #0x04
|
||||
|
||||
//; keep d-cache disabled on Raptor Rev 1.0 silicon
|
||||
orr r3, r3, #0x4000 //;disable dcache
|
||||
MCR p15, 0, r3, c1, c0, 1 //; WCP15_ACTLR r3
|
||||
|
||||
//;End of error and control setting
|
||||
|
||||
//;----------------------------------------------------------------------
|
||||
//; Unlock ETM and read StickyPD to halt the ETM clocks from running.
|
||||
//; This is required for power saving whether the ETM is used or not.
|
||||
//;----------------------------------------------------------------------
|
||||
|
||||
//;Clear ETMOSLSR[LOCK] bit
|
||||
MOV r1, #0x00000000
|
||||
MCR p14, 1, r1, c1, c0, 4 //; WCP14_ETMOSLAR r1
|
||||
|
||||
//;Clear ETMPDSR[STICKYPD] bit
|
||||
MRC p14, 1, r2, c1, c5, 4 //; RCP14_ETMPDSR r2
|
||||
|
||||
/*
|
||||
#ifdef APPSBL_ETM_ENABLE
|
||||
;----------------------------------------------------------------------
|
||||
; Optionally Enable the ETM (Embedded Trace Macro) which is used for debug
|
||||
;----------------------------------------------------------------------
|
||||
|
||||
; enable ETM clock if disabled
|
||||
MRC p15, 7, r1, c15, c0, 5 ; RCP15_CPMR r1
|
||||
ORR r1, r1, #0x00000008
|
||||
MCR p15, 7, r1, c15, c0, 5 ; WCP15_CPMR r1
|
||||
ISB
|
||||
|
||||
; set trigger event to counter1 being zero
|
||||
MOV r3, #0x00000040
|
||||
MCR p14, 1, r3, c0, c2, 0 ; WCP14_ETMTRIGGER r3
|
||||
|
||||
; clear ETMSR
|
||||
MOV r2, #0x00000000
|
||||
MCR p14, 1, r2, c0, c4, 0 ; WCP14_ETMSR r2
|
||||
|
||||
; clear trace enable single address comparator usage
|
||||
MCR p14, 1, r2, c0, c7, 0 ; WCP14_ETMTECR2 r2
|
||||
|
||||
; set trace enable to always
|
||||
MOV r2, #0x0000006F
|
||||
MCR p14, 1, r2, c0, c8, 0 ; WCP14_ETMTEEVR r2
|
||||
|
||||
; clear trace enable address range comparator usage and exclude nothing
|
||||
MOV r2, #0x01000000
|
||||
MCR p14, 1, r2, c0, c9, 0 ; WCP14_ETMTECR1 r2
|
||||
|
||||
; set view data to always
|
||||
MOV r2, #0x0000006F
|
||||
MCR p14, 1, r2, c0, c12, 0 ; WCP14_ETMVDEVR r2
|
||||
|
||||
; clear view data single address comparator usage
|
||||
MOV r2, #0x00000000
|
||||
MCR p14, 1, r2, c0, c13, 0 ; WCP14_ETMVDCR1 r2
|
||||
|
||||
; clear view data address range comparator usage and exclude nothing
|
||||
MOV r2, #0x00010000
|
||||
MCR p14, 1, r2, c0, c15, 0 ; WCP14_ETMVDCR3 r2
|
||||
|
||||
; set counter1 to 194
|
||||
MOV r2, #0x000000C2
|
||||
MCR p14, 1, r2, c0, c0, 5 ; WCP14_ETMCNTRLDVR1 r2
|
||||
|
||||
; set counter1 to never reload
|
||||
MOV r2, #0x0000406F
|
||||
MCR p14, 1, r2, c0, c8, 5 ; WCP14_ETMCNTRLDEVR1 r2
|
||||
|
||||
; set counter1 to decrement every cycle
|
||||
MOV r2, #0x0000006F
|
||||
MCR p14, 1, r2, c0, c4, 5 ; WCP14_ETMCNTENR1 r2
|
||||
|
||||
; Set trace synchronization frequency 1024 bytes
|
||||
MOV r2, #0x00000400
|
||||
MCR p14, 1, r2, c0, c8, 7 ; WCP14_ETMSYNCFR r2
|
||||
|
||||
; Program etm control register
|
||||
; - Set the CPU to ETM clock ratio to 1:1
|
||||
; - Set the ETM to perform data address tracing
|
||||
MOV r2, #0x00002008
|
||||
MCR p14, 1, r2, c0, c0, 0 ; WCP14_ETMCR r2
|
||||
ISB
|
||||
#endif *//* APPSBL_ETM_ENABLE */
|
||||
|
||||
/*
|
||||
#ifdef APPSBL_VFP_ENABLE
|
||||
;----------------------------------------------------------------------
|
||||
; Perform the following operations if you intend to make use of
|
||||
; the VFP/Neon unit. Note that the FMXR instruction requires a CPU ID
|
||||
; indicating the VFP unit is present (i.e.Cortex-A8). .
|
||||
; Some tools will require full double precision floating point support
|
||||
; which will become available in Scorpion pass 2
|
||||
;----------------------------------------------------------------------
|
||||
; allow full access to CP 10 and 11 space for VFP/NEON use
|
||||
MRC p15, 0, r1, c1, c0, 2 ; Read CP Access Control Register
|
||||
ORR r1, r1, #0x00F00000 ; enable full access for p10,11
|
||||
MCR p15, 0, r1, c1, c0, 2 ; Write CPACR
|
||||
|
||||
;make sure the CPACR is complete before continuing
|
||||
ISB
|
||||
|
||||
; Enable VFP itself (certain OSes may want to dynamically set/clear
|
||||
; the enable bit based on the application being executed
|
||||
MOV r1, #0x40000000
|
||||
FMXR FPEXC, r1
|
||||
#endif *//* APPSBL_VFP_ENABLE */
|
||||
|
||||
/* we have no stack, so just tail-call into the SET_SA routine... */
|
||||
b SET_SA
|
||||
|
||||
.ltorg
|
||||
76
platform/qsd8k/debug.c
Normal file
76
platform/qsd8k/debug.c
Normal file
@@ -0,0 +1,76 @@
|
||||
/*
|
||||
* Copyright (c) 2008, Google Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Google, Inc. nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <debug.h>
|
||||
#include <printf.h>
|
||||
#include <arch/arm/dcc.h>
|
||||
#include <dev/uart.h>
|
||||
|
||||
#define DCC_DEBUG 1
|
||||
#define DEBUG_UART 2
|
||||
|
||||
void _dputc(char c)
|
||||
{
|
||||
#if DCC_DEBUG
|
||||
if (c == '\n') {
|
||||
while (dcc_putc('\r') < 0);
|
||||
}
|
||||
while (dcc_putc(c) < 0);
|
||||
#else
|
||||
uart_putc(DEBUG_UART, c);
|
||||
#endif
|
||||
}
|
||||
|
||||
int dgetc(char *c)
|
||||
{
|
||||
#if DCC_DEBUG
|
||||
int n = dcc_getc();
|
||||
if (n < 0) {
|
||||
return -1;
|
||||
} else {
|
||||
*c = n;
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
return uart_getc(DEBUG_UART, 1);
|
||||
#endif
|
||||
}
|
||||
|
||||
void platform_halt(void)
|
||||
{
|
||||
dprintf(INFO, "HALT: spinning forever...\n");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
uint32_t debug_cycle_count(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
45
platform/qsd8k/include/platform/iomap.h
Normal file
45
platform/qsd8k/include/platform/iomap.h
Normal file
@@ -0,0 +1,45 @@
|
||||
/*
|
||||
* Copyright (c) 2008, Google Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Google, Inc. nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _PLATFORM_MSM7K_IOMAP_H_
|
||||
#define _PLATFORM_MSM7K_IOMAP_H_
|
||||
|
||||
#define MSM_UART1_BASE 0xA9A00000
|
||||
#define MSM_UART2_BASE 0xA9B00000
|
||||
#define MSM_UART3_BASE 0xA9C00000
|
||||
|
||||
#define MSM_VIC_BASE 0xAC000000
|
||||
#define MSM_GPT_BASE 0xAC100000
|
||||
#define MSM_CSR_BASE 0xAC100000
|
||||
|
||||
#define MSM_SHARED_BASE 0x01F00000
|
||||
|
||||
#endif
|
||||
131
platform/qsd8k/include/platform/irqs.h
Normal file
131
platform/qsd8k/include/platform/irqs.h
Normal file
@@ -0,0 +1,131 @@
|
||||
/*
|
||||
* Copyright (c) 2008, Google Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Google, Inc. nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _PLATFORM_MSM7K_IRQS_H_
|
||||
#define _PLATFORM_MSM7K_IRQS_H_
|
||||
|
||||
#define INT_A9_M2A_0 0
|
||||
#define INT_A9_M2A_1 1
|
||||
#define INT_A9_M2A_2 2
|
||||
#define INT_A9_M2A_3 3
|
||||
#define INT_A9_M2A_4 4
|
||||
#define INT_A9_M2A_5 5
|
||||
#define INT_A9_M2A_6 6
|
||||
#define INT_GP_TIMER_EXP 7
|
||||
#define INT_DEBUG_TIMER_EXP 8
|
||||
#define INT_SIRC_0 9
|
||||
#define INT_SDC3_0 10
|
||||
#define INT_SDC3_1 11
|
||||
#define INT_SDC4_0 12
|
||||
#define INT_SDC4_1 13
|
||||
#define INT_AD6_EXT_VFR 14
|
||||
#define INT_USB_OTG 15
|
||||
#define INT_MDDI_PRI 16
|
||||
#define INT_MDDI_EXT 17
|
||||
#define INT_MDDI_CLIENT 18
|
||||
#define INT_MDP 19
|
||||
#define INT_GRAPHICS 20
|
||||
#define INT_ADM_AARM 21
|
||||
#define INT_ADSP_A11 22
|
||||
#define INT_ADSP_A9_A11 23
|
||||
#define INT_SDC1_0 24
|
||||
#define INT_SDC1_1 25
|
||||
#define INT_SDC2_0 26
|
||||
#define INT_SDC2_1 27
|
||||
#define INT_KEYSENSE 28
|
||||
#define INT_TCHSCRN_SSBI 29
|
||||
#define INT_TCHSCRN1 30
|
||||
#define INT_TCHSCRN2 31
|
||||
|
||||
#define INT_TCSR_MPRPH_SC1 (32 + 0)
|
||||
#define INT_USB_FS2 (32 + 1)
|
||||
#define INT_PWB_I2C (32 + 2)
|
||||
#define INT_SOFTRESET (32 + 3)
|
||||
#define INT_NAND_WR_ER_DONE (32 + 4)
|
||||
#define INT_NAND_OP_DONE (32 + 5)
|
||||
#define INT_TCSR_MPRPH_SC2 (32 + 6)
|
||||
#define INT_OP_PEN (32 + 7)
|
||||
#define INT_AD_HSSD (32 + 8)
|
||||
#define INT_ARM11_PM (32 + 9)
|
||||
#define INT_SDMA_NON_SECURE (32 + 10)
|
||||
#define INT_TSIF_IRQ (32 + 11)
|
||||
#define INT_UART1DM_IRQ (32 + 12)
|
||||
#define INT_UART1DM_RX (32 + 13)
|
||||
#define INT_SDMA_SECURE (32 + 14)
|
||||
#define INT_SI2S_SLAVE (32 + 15)
|
||||
#define INT_SC_I2CPU (32 + 16)
|
||||
#define INT_SC_DBG_RDTRFULL (32 + 17)
|
||||
#define INT_SC_DBG_WDTRFULL (32 + 18)
|
||||
#define INT_SCPLL_CTL_DONE (32 + 19)
|
||||
#define INT_UART2DM_IRQ (32 + 20)
|
||||
#define INT_UART2DM_RX (32 + 21)
|
||||
#define INT_VDC_MEC (32 + 22)
|
||||
#define INT_VDC_DB (32 + 23)
|
||||
#define INT_VDC_AXI (32 + 24)
|
||||
#define INT_VFE (32 + 25)
|
||||
#define INT_USB_HS (32 + 26)
|
||||
#define INT_AUDIO_OUT0 (32 + 27)
|
||||
#define INT_AUDIO_OUT1 (32 + 28)
|
||||
#define INT_CRYPTO (32 + 29)
|
||||
#define INT_AD6M_IDLE (32 + 30)
|
||||
#define INT_SIRC_1 (32 + 31)
|
||||
|
||||
/* secondary interrupt controller */
|
||||
|
||||
#define INT_UART1_IRQ (64 + 0)
|
||||
#define INT_UART2_IRQ (64 + 1)
|
||||
#define INT_UART3_IRQ (64 + 2)
|
||||
#define INT_UART1_RX (64 + 3)
|
||||
#define INT_UART2_RX (64 + 4)
|
||||
#define INT_UART3_RX (64 + 5)
|
||||
#define INT_SPI_INPUT (64 + 6)
|
||||
#define INT_SPI_OUTPUT (64 + 7)
|
||||
#define INT_SPI_ERROR (64 + 8)
|
||||
#define INT_GPIO1_SHADOW (64 + 9)
|
||||
#define INT_GPIO2_SHADOW (64 + 10)
|
||||
#define INT_GPIO1_SECURE (64 + 11)
|
||||
#define INT_GPIO2_SECURE (64 + 12)
|
||||
#define INT_SC_AVS_SVIC (64 + 13)
|
||||
#define INT_SC_AVS_REQ_UP (64 + 14)
|
||||
#define INT_SC_AVS_REQ_DOWN (64 + 15)
|
||||
#define INT_PBUS_ERR (64 + 16)
|
||||
#define INT_AXI (64 + 17)
|
||||
#define INT_SMI (64 + 18)
|
||||
#define INT_EBI (64 + 19)
|
||||
#define INT_IMEM (64 + 20)
|
||||
#define INT_SC_TEMP_SENSOR (64 + 21)
|
||||
#define INT_TV_ENC (64 + 22)
|
||||
|
||||
#define MSM_IRQ_BIT(irq) (1 << ((irq) & 31))
|
||||
|
||||
#define NR_IRQS 64
|
||||
|
||||
#endif
|
||||
159
platform/qsd8k/interrupts.c
Normal file
159
platform/qsd8k/interrupts.c
Normal file
@@ -0,0 +1,159 @@
|
||||
/*
|
||||
* Copyright (c) 2008, Google Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Google, Inc. nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <debug.h>
|
||||
#include <arch/arm.h>
|
||||
#include <reg.h>
|
||||
#include <kernel/thread.h>
|
||||
#include <platform/interrupts.h>
|
||||
|
||||
#include <platform/irqs.h>
|
||||
#include <platform/iomap.h>
|
||||
|
||||
#define VIC_REG(off) (MSM_VIC_BASE + (off))
|
||||
|
||||
#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */
|
||||
#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
|
||||
#define VIC_INT_EN0 VIC_REG(0x0010)
|
||||
#define VIC_INT_EN1 VIC_REG(0x0014)
|
||||
#define VIC_INT_ENCLEAR0 VIC_REG(0x0020)
|
||||
#define VIC_INT_ENCLEAR1 VIC_REG(0x0024)
|
||||
#define VIC_INT_ENSET0 VIC_REG(0x0030)
|
||||
#define VIC_INT_ENSET1 VIC_REG(0x0034)
|
||||
#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
|
||||
#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
|
||||
#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
|
||||
#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
|
||||
#define VIC_NO_PEND_VAL VIC_REG(0x0060)
|
||||
#define VIC_INT_MASTEREN VIC_REG(0x0068) /* 1: IRQ, 2: FIQ */
|
||||
#define VIC_CONFIG VIC_REG(0x006C) /* 1: USE ARM1136 VIC */
|
||||
#define VIC_SECURITY0 VIC_REG(0x0070)
|
||||
#define VIC_SECURITY1 VIC_REG(0x0074)
|
||||
#define VIC_IRQ_STATUS0 VIC_REG(0x0080)
|
||||
#define VIC_IRQ_STATUS1 VIC_REG(0x0084)
|
||||
#define VIC_FIQ_STATUS0 VIC_REG(0x0090)
|
||||
#define VIC_FIQ_STATUS1 VIC_REG(0x0094)
|
||||
#define VIC_RAW_STATUS0 VIC_REG(0x00A0)
|
||||
#define VIC_RAW_STATUS1 VIC_REG(0x00A4)
|
||||
#define VIC_INT_CLEAR0 VIC_REG(0x00B0)
|
||||
#define VIC_INT_CLEAR1 VIC_REG(0x00B4)
|
||||
#define VIC_SOFTINT0 VIC_REG(0x00C0)
|
||||
#define VIC_SOFTINT1 VIC_REG(0x00C4)
|
||||
#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */
|
||||
#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
|
||||
#define VIC_IRQ_VEC_WR VIC_REG(0x00D8)
|
||||
#define VIC_FIQ_VEC_RD VIC_REG(0x00DC) /* pending int # */
|
||||
#define VIC_FIQ_VEC_PEND_RD VIC_REG(0x00E0) /* pending vector addr */
|
||||
#define VIC_FIQ_VEC_WR VIC_REG(0x00E4)
|
||||
#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E8)
|
||||
#define VIC_IRQ_IN_STACK VIC_REG(0x00EC)
|
||||
#define VIC_FIQ_IN_SERVICE VIC_REG(0x00F0)
|
||||
#define VIC_FIQ_IN_STACK VIC_REG(0x00F4)
|
||||
#define VIC_TEST_BUS_SEL VIC_REG(0x00F8)
|
||||
|
||||
#define SIRC_REG(off) (MSM_SIRC_BASE + (off))
|
||||
|
||||
#define SIRC_INT_SELECT SIRC_REG(0x0000) /* 0: IRQ0 1: IRQ1 */
|
||||
#define SIRC_INT_ENABLE SIRC_REG(0x0004)
|
||||
#define SIRC_INT_ENCLEAR SIRC_REG(0x0008)
|
||||
#define SIRC_INT_ENSET SIRC_REG(0x000C)
|
||||
#define SIRC_INT_TYPE SIRC_REG(0x0010) /* 1: EDGE, 0: LEVEL */
|
||||
#define SIRC_INT_POLARITY SIRC_REG(0x0014) /* 1: NEG, 0: POS */
|
||||
#define SIRC_SECURITY SIRC_REG(0x0018) /* 0: SEC, 1: NSEC */
|
||||
#define SIRC_IRQ0_STATUS SIRC_REG(0x001C)
|
||||
#define SIRC_IRQ1_STATUS SIRC_REG(0x0020)
|
||||
#define SIRC_RAW_STATUS SIRC_REG(0x0024)
|
||||
|
||||
struct ihandler {
|
||||
int_handler func;
|
||||
void *arg;
|
||||
};
|
||||
|
||||
static struct ihandler handler[NR_IRQS];
|
||||
|
||||
void platform_init_interrupts(void)
|
||||
{
|
||||
writel(0xffffffff, VIC_INT_CLEAR0);
|
||||
writel(0xffffffff, VIC_INT_CLEAR1);
|
||||
writel(0, VIC_INT_SELECT0);
|
||||
writel(0, VIC_INT_SELECT1);
|
||||
writel(0xffffffff, VIC_INT_TYPE0);
|
||||
writel(0xffffffff, VIC_INT_TYPE1);
|
||||
writel(0, VIC_CONFIG);
|
||||
writel(1, VIC_INT_MASTEREN);
|
||||
}
|
||||
|
||||
enum handler_return platform_irq(struct arm_iframe *frame)
|
||||
{
|
||||
unsigned num;
|
||||
enum handler_return ret;
|
||||
num = readl(VIC_IRQ_VEC_RD);
|
||||
num = readl(VIC_IRQ_VEC_PEND_RD);
|
||||
if (num > NR_IRQS)
|
||||
return 0;
|
||||
writel(1 << (num & 31), (num > 31) ? VIC_INT_CLEAR1 : VIC_INT_CLEAR0);
|
||||
ret = handler[num].func(handler[num].arg);
|
||||
writel(0, VIC_IRQ_VEC_WR);
|
||||
return ret;
|
||||
}
|
||||
|
||||
void platform_fiq(struct arm_iframe *frame)
|
||||
{
|
||||
PANIC_UNIMPLEMENTED;
|
||||
}
|
||||
|
||||
status_t mask_interrupt(unsigned int vector)
|
||||
{
|
||||
unsigned reg = (vector > 31) ? VIC_INT_ENCLEAR1 : VIC_INT_ENCLEAR0;
|
||||
unsigned bit = 1 << (vector & 31);
|
||||
writel(bit, reg);
|
||||
return 0;
|
||||
}
|
||||
|
||||
status_t unmask_interrupt(unsigned int vector)
|
||||
{
|
||||
unsigned reg = (vector > 31) ? VIC_INT_ENSET1 : VIC_INT_ENSET0;
|
||||
unsigned bit = 1 << (vector & 31);
|
||||
writel(bit, reg);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void register_int_handler(unsigned int vector, int_handler func, void *arg)
|
||||
{
|
||||
if (vector >= NR_IRQS)
|
||||
return;
|
||||
|
||||
enter_critical_section();
|
||||
handler[vector].func = func;
|
||||
handler[vector].arg = arg;
|
||||
exit_critical_section();
|
||||
}
|
||||
|
||||
151
platform/qsd8k/lcdc.c
Normal file
151
platform/qsd8k/lcdc.c
Normal file
@@ -0,0 +1,151 @@
|
||||
/*
|
||||
* Copyright (c) 2008, Google Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <debug.h>
|
||||
#include <stdlib.h>
|
||||
#include <reg.h>
|
||||
#include <platform/iomap.h>
|
||||
|
||||
#define MSM_MDP_BASE1 0xAA200000
|
||||
|
||||
unsigned fb_width = 0;
|
||||
unsigned fb_height = 0;
|
||||
|
||||
static unsigned short *FB;
|
||||
|
||||
|
||||
#define LCDC_PIXCLK_IN_PS 26
|
||||
#define LCDC_FB_PHYS 0x16600000
|
||||
#define LCDC_FB_BPP 16
|
||||
|
||||
#if 1
|
||||
/* SURF */
|
||||
#define LCDC_FB_WIDTH 800
|
||||
#define LCDC_FB_HEIGHT 480
|
||||
|
||||
#define LCDC_HSYNC_PULSE_WIDTH_DCLK 60
|
||||
#define LCDC_HSYNC_BACK_PORCH_DCLK 81
|
||||
#define LCDC_HSYNC_FRONT_PORCH_DCLK 81
|
||||
#define LCDC_HSYNC_SKEW_DCLK 0
|
||||
|
||||
#define LCDC_VSYNC_PULSE_WIDTH_LINES 2
|
||||
#define LCDC_VSYNC_BACK_PORCH_LINES 20
|
||||
#define LCDC_VSYNC_FRONT_PORCH_LINES 27
|
||||
|
||||
#else
|
||||
/* FFA */
|
||||
#define LCDC_FB_WIDTH 480
|
||||
#define LCDC_FB_HEIGHT 640
|
||||
|
||||
#define LCDC_HSYNC_PULSE_WIDTH_DCLK 60
|
||||
#define LCDC_HSYNC_BACK_PORCH_DCLK 144
|
||||
#define LCDC_HSYNC_FRONT_PORCH_DCLK 33
|
||||
#define LCDC_HSYNC_SKEW_DCLK 0
|
||||
|
||||
#define LCDC_VSYNC_PULSE_WIDTH_LINES 2
|
||||
#define LCDC_VSYNC_BACK_PORCH_LINES 2
|
||||
#define LCDC_VSYNC_FRONT_PORCH_LINES 2
|
||||
|
||||
#endif
|
||||
|
||||
#define BIT(x) (1<<(x))
|
||||
#define DMA_DSTC0G_8BITS (BIT(1)|BIT(0))
|
||||
#define DMA_DSTC1B_8BITS (BIT(3)|BIT(2))
|
||||
#define DMA_DSTC2R_8BITS (BIT(5)|BIT(4))
|
||||
#define CLR_G 0x0
|
||||
#define CLR_B 0x1
|
||||
#define CLR_R 0x2
|
||||
#define MDP_GET_PACK_PATTERN(a,x,y,z,bit) (((a)<<(bit*3))|((x)<<(bit*2))|((y)<<bit)|(z))
|
||||
#define DMA_PACK_ALIGN_LSB 0
|
||||
#define DMA_PACK_PATTERN_RGB \
|
||||
(MDP_GET_PACK_PATTERN(0,CLR_R,CLR_G,CLR_B,2)<<8)
|
||||
#define DMA_DITHER_EN BIT(24)
|
||||
#define DMA_OUT_SEL_LCDC BIT(20)
|
||||
#define DMA_IBUF_FORMAT_RGB565 BIT(25)
|
||||
|
||||
void lcdc_clock_init(unsigned rate);
|
||||
|
||||
void lcdc_init(void)
|
||||
{
|
||||
unsigned n;
|
||||
|
||||
dprintf(INFO, "lcdc_init()\n");
|
||||
|
||||
fb_width = LCDC_FB_WIDTH;
|
||||
fb_height = LCDC_FB_HEIGHT;
|
||||
dprintf(INFO, "panel is %d x %d\n", fb_width, fb_height);
|
||||
|
||||
FB = LCDC_FB_PHYS; //alloc(2 * fb_width * fb_height);
|
||||
|
||||
FB = memalign(4096, 2 * fb_width * fb_height);
|
||||
dprintf(INFO, "FB %p\n", FB);
|
||||
|
||||
lcdc_clock_init(1000000000 / LCDC_PIXCLK_IN_PS);
|
||||
|
||||
writel(FB, MSM_MDP_BASE1 + 0x90008);
|
||||
writel((LCDC_FB_HEIGHT << 16) | LCDC_FB_WIDTH, MSM_MDP_BASE1 + 0x90004);
|
||||
writel(LCDC_FB_WIDTH * LCDC_FB_BPP / 8, MSM_MDP_BASE1 + 0x9000c);
|
||||
writel(0, MSM_MDP_BASE1 + 0x90010);
|
||||
|
||||
writel(DMA_PACK_ALIGN_LSB|DMA_PACK_PATTERN_RGB|DMA_DITHER_EN|DMA_OUT_SEL_LCDC|
|
||||
DMA_IBUF_FORMAT_RGB565|DMA_DSTC0G_8BITS|DMA_DSTC1B_8BITS|DMA_DSTC2R_8BITS,
|
||||
MSM_MDP_BASE1 + 0x90000);
|
||||
|
||||
int hsync_period = LCDC_HSYNC_PULSE_WIDTH_DCLK + LCDC_HSYNC_BACK_PORCH_DCLK + LCDC_FB_WIDTH + LCDC_HSYNC_FRONT_PORCH_DCLK;
|
||||
int vsync_period = (LCDC_VSYNC_PULSE_WIDTH_LINES + LCDC_VSYNC_BACK_PORCH_LINES + LCDC_FB_HEIGHT + LCDC_VSYNC_FRONT_PORCH_LINES) * hsync_period;
|
||||
int hsync_ctrl = (hsync_period << 16) | LCDC_HSYNC_PULSE_WIDTH_DCLK;
|
||||
int hsync_start_x = LCDC_HSYNC_PULSE_WIDTH_DCLK + LCDC_HSYNC_BACK_PORCH_DCLK;
|
||||
int hsync_end_x = hsync_period - LCDC_HSYNC_FRONT_PORCH_DCLK - 1;
|
||||
int display_hctl = (hsync_end_x << 16) | hsync_start_x;
|
||||
int display_vstart= (LCDC_VSYNC_PULSE_WIDTH_LINES + LCDC_VSYNC_BACK_PORCH_LINES) * hsync_period + LCDC_HSYNC_SKEW_DCLK;
|
||||
int display_vend = vsync_period - (LCDC_VSYNC_FRONT_PORCH_LINES * hsync_period) + LCDC_HSYNC_SKEW_DCLK - 1;
|
||||
|
||||
writel((hsync_period << 16) | LCDC_HSYNC_PULSE_WIDTH_DCLK, MSM_MDP_BASE1 + 0xe0004);
|
||||
writel(vsync_period, MSM_MDP_BASE1 + 0xe0008);
|
||||
writel(LCDC_VSYNC_PULSE_WIDTH_LINES * hsync_period, MSM_MDP_BASE1 + 0xe000c);
|
||||
writel(display_hctl, MSM_MDP_BASE1 + 0xe0010);
|
||||
writel(display_vstart, MSM_MDP_BASE1 + 0xe0014);
|
||||
writel(display_vend, MSM_MDP_BASE1 + 0xe0018);
|
||||
writel(0, MSM_MDP_BASE1 + 0xe0028);
|
||||
writel(0xff, MSM_MDP_BASE1 + 0xe002c);
|
||||
writel(LCDC_HSYNC_SKEW_DCLK, MSM_MDP_BASE1 + 0xe0030);
|
||||
writel(0, MSM_MDP_BASE1 + 0xe0038);
|
||||
writel(0, MSM_MDP_BASE1 + 0xe001c);
|
||||
writel(0, MSM_MDP_BASE1 + 0xe0020);
|
||||
writel(0, MSM_MDP_BASE1 + 0xe0024);
|
||||
|
||||
writel(1, MSM_MDP_BASE1 + 0xe0000);
|
||||
|
||||
for(n = 0; n < (fb_width * fb_height); n++) FB[n] = 0x01f0;
|
||||
}
|
||||
|
||||
void *mddi_framebuffer(void)
|
||||
{
|
||||
return FB;
|
||||
}
|
||||
|
||||
58
platform/qsd8k/platform.c
Normal file
58
platform/qsd8k/platform.c
Normal file
@@ -0,0 +1,58 @@
|
||||
/*
|
||||
* Copyright (c) 2008, Google Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Google, Inc. nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <debug.h>
|
||||
|
||||
#include <kernel/thread.h>
|
||||
#include <platform/debug.h>
|
||||
|
||||
void platform_init_interrupts(void);
|
||||
void platform_init_timer();
|
||||
|
||||
void uart3_clock_init(void);
|
||||
void uart_init(void);
|
||||
|
||||
void lcdc_init(void);
|
||||
|
||||
void platform_early_init(void)
|
||||
{
|
||||
// uart3_clock_init();
|
||||
// uart_init();
|
||||
|
||||
platform_init_interrupts();
|
||||
platform_init_timer();
|
||||
}
|
||||
|
||||
void platform_init(void)
|
||||
{
|
||||
dprintf(INFO, "platform_init()\n");
|
||||
lcdc_init();
|
||||
}
|
||||
22
platform/qsd8k/rules.mk
Normal file
22
platform/qsd8k/rules.mk
Normal file
@@ -0,0 +1,22 @@
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
ARCH := arm
|
||||
ARM_CPU := cortex-a8
|
||||
#arm1136j-s
|
||||
CPU := generic
|
||||
|
||||
DEFINES += WITH_CPU_EARLY_INIT=1 MEMBASE=0
|
||||
|
||||
INCLUDES += -I$(LOCAL_DIR)/include
|
||||
|
||||
OBJS += \
|
||||
$(LOCAL_DIR)/arch_init.o \
|
||||
$(LOCAL_DIR)/platform.o \
|
||||
$(LOCAL_DIR)/interrupts.o \
|
||||
$(LOCAL_DIR)/debug.o \
|
||||
$(LOCAL_DIR)/lcdc.o
|
||||
|
||||
LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
|
||||
|
||||
include platform/msm_shared/rules.mk
|
||||
|
||||
10
target/surf-qsd8k/rules.mk
Normal file
10
target/surf-qsd8k/rules.mk
Normal file
@@ -0,0 +1,10 @@
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
INCLUDES += -I$(LOCAL_DIR)/include
|
||||
|
||||
PLATFORM := qsd8k
|
||||
|
||||
MEMBASE := 0x00000000 # SMI
|
||||
MEMSIZE := 0x00800000 # 8MB
|
||||
|
||||
DEFINES += SDRAM_SIZE=$(MEMSIZE)
|
||||
Reference in New Issue
Block a user