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[arch][mmu] clean up page size definitions in each arch's defines.h

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No real functional change except how the smaller ARCH_DEFAULT_PAGE_SIZE
is now computed and set in defines.h instead of rules.mk for arch/arm to
be consistent with the other arch that has a large/small build (riscv).
This commit is contained in:
Travis Geiselbrecht
2025-08-31 19:16:58 -07:00
parent 0a8a4354a9
commit cc9c3a053c
13 changed files with 78 additions and 78 deletions
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1
arch/arm/arm/start.S
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@@ -8,6 +8,7 @@
#include <lk/asm.h>
#include <arch/arm/cores.h>
#include <arch/arm/mmu.h>
#include <arch/defines.h>
#if WITH_KERNEL_VM
#include <kernel/vm.h>

9
arch/arm/include/arch/defines.h
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@@ -9,8 +9,14 @@
#define __ARCH_CPU_H
/* arm specific stuff */
#define PAGE_SIZE 4096
#define PAGE_SIZE_SHIFT 12
#define PAGE_SIZE (1U << PAGE_SIZE_SHIFT)
#if ARCH_ARM_EMBEDDED
#define ARCH_DEFAULT_STACK_SIZE 1024
#else
#define ARCH_DEFAULT_STACK_SIZE PAGE_SIZE
#endif
#if ARM_CPU_ARM7
/* irrelevant, no consistent cache */
@@ -42,4 +48,3 @@
#endif
#endif

5
arch/arm/rules.mk
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@@ -255,9 +255,6 @@ MODULE_FLOAT_SRCS += \
MODULE_ARM_OVERRIDE_SRCS := \
$(LOCAL_DIR)/arm/arch.c
GLOBAL_DEFINES += \
ARCH_DEFAULT_STACK_SIZE=4096
ARCH_OPTFLAGS := -O2
WITH_LINKER_GC ?= 1
@@ -319,7 +316,7 @@ MODULE_SRCS += \
# we're building for small binaries
GLOBAL_DEFINES += \
ARM_ONLY_THUMB=1 \
ARCH_DEFAULT_STACK_SIZE=1024 \
ARCH_ARM_EMBEDDED=1 \
SMP_MAX_CPUS=1
MODULE_DEPS += \

13
arch/arm64/include/arch/defines.h
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@@ -7,9 +7,9 @@
*/
#pragma once
#define SHIFT_4K (12)
#define SHIFT_16K (14)
#define SHIFT_64K (16)
#define SHIFT_4K (12)
#define SHIFT_16K (14)
#define SHIFT_64K (16)
/* arm specific stuff */
#ifdef ARM64_LARGE_PAGESIZE_64K
@@ -19,13 +19,16 @@
#else
#define PAGE_SIZE_SHIFT (SHIFT_4K)
#endif
#define USER_PAGE_SIZE_SHIFT SHIFT_4K
#define USER_PAGE_SIZE_SHIFT PAGE_SIZE_SHIFT
#define PAGE_SIZE (1UL << PAGE_SIZE_SHIFT)
#define PAGE_SIZE (1UL << PAGE_SIZE_SHIFT)
#define USER_PAGE_SIZE (1UL << USER_PAGE_SIZE_SHIFT)
// TODO: for all practical purposes the default should be 64
#if ARM64_CPU_CORTEX_A53 || ARM64_CPU_CORTEX_A57 || ARM64_CPU_CORTEX_A72
#define CACHE_LINE 64
#else
#define CACHE_LINE 32
#endif
#define ARCH_DEFAULT_STACK_SIZE PAGE_SIZE

3
arch/arm64/rules.mk
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@@ -24,9 +24,6 @@ MODULE_SRCS += \
$(LOCAL_DIR)/arm/faults.c \
$(LOCAL_DIR)/arm/dcc.S
GLOBAL_DEFINES += \
ARCH_DEFAULT_STACK_SIZE=4096
# if its requested we build with SMP, arm generically supports 4 cpus
ifeq ($(WITH_SMP),1)
SMP_MAX_CPUS ?= 4

4
arch/m68k/include/arch/defines.h
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@@ -7,10 +7,10 @@
*/
#pragma once
#define PAGE_SIZE 4096
#define PAGE_SIZE_SHIFT 12
#define PAGE_SIZE (1U << PAGE_SIZE_SHIFT)
// XXX is this right?
#define CACHE_LINE 32
#define ARCH_DEFAULT_STACK_SIZE 4096
#define ARCH_DEFAULT_STACK_SIZE PAGE_SIZE

4
arch/microblaze/include/arch/defines.h
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@@ -7,10 +7,10 @@
*/
#pragma once
#define PAGE_SIZE 4096
#define PAGE_SIZE_SHIFT 12
#define PAGE_SIZE (1U << PAGE_SIZE_SHIFT)
// XXX is this right?
#define CACHE_LINE 32
#define ARCH_DEFAULT_STACK_SIZE 4096
#define ARCH_DEFAULT_STACK_SIZE PAGE_SIZE

4
arch/mips/include/arch/defines.h
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@@ -7,10 +7,10 @@
*/
#pragma once
#define PAGE_SIZE 4096
#define PAGE_SIZE_SHIFT 12
#define PAGE_SIZE (1U << PAGE_SIZE_SHIFT)
// XXX is this right?
#define CACHE_LINE 32
#define ARCH_DEFAULT_STACK_SIZE 4096
#define ARCH_DEFAULT_STACK_SIZE PAGE_SIZE

4
arch/or1k/include/arch/defines.h
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@@ -7,10 +7,10 @@
*/
#pragma once
#define PAGE_SIZE 8192
#define PAGE_SIZE_SHIFT 13
#define PAGE_SIZE (1U << PAGE_SIZE_SHIFT)
/* Cache line can be configured, but this is max */
#define CACHE_LINE 32
#define ARCH_DEFAULT_STACK_SIZE 8192
#define ARCH_DEFAULT_STACK_SIZE PAGE_SIZE

4
arch/riscv/include/arch/defines.h
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@@ -7,8 +7,8 @@
*/
#pragma once
#define PAGE_SIZE 4096
#define PAGE_SIZE_SHIFT 12
#define PAGE_SIZE (1U << PAGE_SIZE_SHIFT)
// XXX is this right?
#define CACHE_LINE 32
@@ -16,5 +16,5 @@
#if ARCH_RISCV_EMBEDDED
#define ARCH_DEFAULT_STACK_SIZE 1024
#else
#define ARCH_DEFAULT_STACK_SIZE 4096
#define ARCH_DEFAULT_STACK_SIZE PAGE_SIZE
#endif

13
arch/x86/include/arch/defines.h
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@@ -8,23 +8,22 @@
*/
#pragma once
#define PAGE_SIZE 4096
#define PAGE_SIZE_SHIFT 12
#define PAGE_SIZE (1UL << PAGE_SIZE_SHIFT)
#define CACHE_LINE 64
#define ARCH_DEFAULT_STACK_SIZE 8192
#define DEFAULT_TSS 4096
#define ARCH_DEFAULT_STACK_SIZE (PAGE_SIZE * 2)
#define DEFAULT_TSS PAGE_SIZE
/* based on how start.S sets up the physmap */
#if ARCH_X86_64
#define PHYSMAP_SIZE (64ULL*1024*1024*1024)
#define PHYSMAP_SIZE (64ULL * 1024 * 1024 * 1024)
#elif X86_LEGACY
/* Only map the first 16MB on legacy x86 due to page table usage
* due to lack of 4MB pages. */
#define PHYSMAP_SIZE (16ULL*1024*1024)
#define PHYSMAP_SIZE (16ULL * 1024 * 1024)
#elif ARCH_X86_32
/* Map 1GB by default for x86-32 */
#define PHYSMAP_SIZE (1ULL*1024*1024*1024)
#define PHYSMAP_SIZE (1ULL * 1024 * 1024 * 1024)
#endif

91
arch/x86/include/arch/x86/mmu.h
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@@ -8,21 +8,23 @@
*/
#pragma once
#include <arch/defines.h>
/* top level defines for the x86 mmu */
/* NOTE: the top part can be included from assembly */
#define KB (1024UL)
#define MB (1024UL*1024UL)
#define GB (1024UL*1024UL*1024UL)
#define KB (1024UL)
#define MB (1024UL * 1024UL)
#define GB (1024UL * 1024UL * 1024UL)
#define X86_MMU_PG_P 0x001 /* P Valid */
#define X86_MMU_PG_RW 0x002 /* R/W Read/Write */
#define X86_MMU_PG_U 0x004 /* U/S User/Supervisor */
#define X86_MMU_PG_PS 0x080 /* PS Page size (0=4k,1=4M) */
#define X86_MMU_PG_PTE_PAT 0x080 /* PAT PAT index */
#define X86_MMU_PG_G 0x100 /* G Global */
#define X86_MMU_CLEAR 0x0
#define X86_DIRTY_ACCESS_MASK 0xf9f
#define X86_MMU_CACHE_DISABLE 0x010 /* C Cache disable */
#define X86_MMU_PG_P 0x001 /* P Valid */
#define X86_MMU_PG_RW 0x002 /* R/W Read/Write */
#define X86_MMU_PG_U 0x004 /* U/S User/Supervisor */
#define X86_MMU_PG_PS 0x080 /* PS Page size (0=4k,1=4M) */
#define X86_MMU_PG_PTE_PAT 0x080 /* PAT PAT index */
#define X86_MMU_PG_G 0x100 /* G Global */
#define X86_MMU_CLEAR 0x0
#define X86_DIRTY_ACCESS_MASK 0xf9f
#define X86_MMU_CACHE_DISABLE 0x010 /* C Cache disable */
#if !X86_LEGACY
/* default flags for inner page directory entries */
@@ -35,57 +37,55 @@
#define X86_KERNEL_PT_FLAGS (X86_MMU_PG_RW | X86_MMU_PG_P)
#endif
#define PAGE_SIZE 4096
#define PAGE_DIV_SHIFT 12
#define PAGE_DIV_SHIFT PAGE_SIZE_SHIFT
#if ARCH_X86_64
/* PAE mode */
#define X86_PDPT_ADDR_MASK (0x00000000ffffffe0ul)
#define X86_PG_FRAME (0xfffffffffffff000ul)
#define X86_PHY_ADDR_MASK (0x000ffffffffffffful)
#define X86_FLAGS_MASK (0x8000000000000ffful)
#define X86_PTE_NOT_PRESENT (0xFFFFFFFFFFFFFFFEul)
#define X86_2MB_PAGE_FRAME (0x000fffffffe00000ul)
#define PAGE_OFFSET_MASK_4KB (0x0000000000000ffful)
#define PAGE_OFFSET_MASK_2MB (0x00000000001ffffful)
#define X86_MMU_PG_NX (1ULL << 63)
#define X86_PDPT_ADDR_MASK (0x00000000ffffffe0ul)
#define X86_PG_FRAME (0xfffffffffffff000ul)
#define X86_PHY_ADDR_MASK (0x000ffffffffffffful)
#define X86_FLAGS_MASK (0x8000000000000ffful)
#define X86_PTE_NOT_PRESENT (0xFFFFFFFFFFFFFFFEul)
#define X86_2MB_PAGE_FRAME (0x000fffffffe00000ul)
#define PAGE_OFFSET_MASK_4KB (0x0000000000000ffful)
#define PAGE_OFFSET_MASK_2MB (0x00000000001ffffful)
#define X86_MMU_PG_NX (1ULL << 63)
#if ARCH_X86_64
#define X86_PAGING_LEVELS 4
#define PML4_SHIFT 39
#define X86_PAGING_LEVELS 4
#define PML4_SHIFT 39
#else
#define X86_PAGING_LEVELS 3
#define X86_PAGING_LEVELS 3
#endif
#define PDP_SHIFT 30
#define PD_SHIFT 21
#define PT_SHIFT 12
#define ADDR_OFFSET 9
#define PDPT_ADDR_OFFSET 2
#define NO_OF_PT_ENTRIES 512
#define PDP_SHIFT 30
#define PD_SHIFT 21
#define PT_SHIFT 12
#define ADDR_OFFSET 9
#define PDPT_ADDR_OFFSET 2
#define NO_OF_PT_ENTRIES 512
#else
/* non PAE mode */
#define X86_PG_FRAME (0xfffff000)
#define X86_FLAGS_MASK (0x00000fff)
#define X86_PTE_NOT_PRESENT (0xfffffffe)
#define X86_4MB_PAGE_FRAME (0xffc00000)
#define PAGE_OFFSET_MASK_4KB (0x00000fff)
#define PAGE_OFFSET_MASK_4MB (0x003fffff)
#define NO_OF_PT_ENTRIES 1024
#define X86_PAGING_LEVELS 2
#define PD_SHIFT 22
#define PT_SHIFT 12
#define ADDR_OFFSET 10
#define X86_PG_FRAME (0xfffff000)
#define X86_FLAGS_MASK (0x00000fff)
#define X86_PTE_NOT_PRESENT (0xfffffffe)
#define X86_4MB_PAGE_FRAME (0xffc00000)
#define PAGE_OFFSET_MASK_4KB (0x00000fff)
#define PAGE_OFFSET_MASK_4MB (0x003fffff)
#define NO_OF_PT_ENTRIES 1024
#define X86_PAGING_LEVELS 2
#define PD_SHIFT 22
#define PT_SHIFT 12
#define ADDR_OFFSET 10
#endif
/* C defines below */
#ifndef ASSEMBLY
#include <sys/types.h>
#include <lk/compiler.h>
#include <sys/types.h>
__BEGIN_CDECLS
@@ -100,7 +100,6 @@ enum page_table_levels {
#endif
};
struct map_range {
vaddr_t start_vaddr;
paddr_t start_paddr; /* Physical address in the PAE mode is 32 bits wide */

1
top/main.c
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@@ -23,7 +23,6 @@
#include <lk/debug.h>
#include <lk/init.h>
#include <platform.h>
#include <string.h>
#include <target.h>
/* saved boot arguments from whoever loaded the system */