WIP [target][visionfive2] Add initial support for a VisionFive 2 RISC-V board

Still TODO:
-Set the timer rate properly
-Fix nonzero based hart secondary cpu boot
-Try to parse the device tree for some information

arch/riscv/mp.c

@@ -152,16 +152,27 @@ void riscv_set_secondary_count(int count) {
 
 // start any secondary cpus we are set to start. called on the boot processor
 void riscv_boot_secondaries(void) {
+    // if theres nothing to start, abort here
+    if (secondaries_to_init == 0) {
+        dprintf(INFO, "RISCV: No secondary harts to start\n");
+        return;
+    }
+
     lk_init_secondary_cpus(secondaries_to_init);
 
 #if RISCV_M_MODE
     dprintf(INFO, "RISCV: Releasing %d secondary harts from purgatory\n", secondaries_to_init);
 #else
     uint boot_hart = riscv_current_hart();
+    dprintf(INFO, "RISCV: Going to try to start %d secondary harts\n", secondaries_to_init);
 
     // use SBI HSM to boot the secondaries
     // TODO: handle the range of harts we should consider, since they
-    // may not be zero based
+    // may not be zero based.
+    // Currently, starts from 0 and tries to start one extra core, with the idea
+    // that boot_hart should be one of them. This algorithm is somewhat broken, but
+    // works in the case of harts being 0-N and the boot hart being nonzero (but within [0...N]).
+    // Doesn't currently handle skipping cpus we shouldn't boot (like HART 0 on some machines)
     for (uint i = 0; i <= (uint)secondaries_to_init; i++) {
         // skip the boot hart
         if (i != boot_hart) {