WIP [target][visionfive2] Add initial support for a VisionFive 2 RISC-V board

Still TODO:
-Set the timer rate properly
-Fix nonzero based hart secondary cpu boot
-Try to parse the device tree for some information

.github/workflows/github-ci.yml

@@ -43,6 +43,7 @@ jobs:
           - pico-test
           - sifive-e-test
           - sifive-unleashed-test
+          - visionfive2-test
           - rosco-m68k-test
         exclude:
           # no toolchain for 7.5.0 for or1k