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[dev][interrupt][arm_gic] Fix fiq code to get cpu number from arch_curr_cpu_num

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Fixes fiq support on multicluster systems.

Change-Id: If19a78b580eec79b7194ea511f0dcd22bc18fd83
This commit is contained in:
Arve Hjønnevåg
2015-05-13 16:47:19 -07:00
parent e07de0831a
commit c027dbd0d4
1 changed files with 12 additions and 16 deletions
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28
dev/interrupt/arm_gic/arm_gic.c
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@@ -20,6 +20,7 @@
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/ */
#include <assert.h>
#include <bits.h> #include <bits.h>
#include <err.h> #include <err.h>
#include <sys/types.h> #include <sys/types.h>
@@ -515,19 +516,6 @@ long smc_intc_request_fiq(smc32_args_t *args)
return NO_ERROR; return NO_ERROR;
} }
static uint32_t read_mpidr(void)
{
int mpidr;
#if ARCH_ARM64
mpidr = ARM64_READ_SYSREG(mpidr_el1);
#else
__asm__ volatile("mrc p15, 0, %0, c0, c0, 5"
: "=r" (mpidr)
);
#endif
return mpidr;
}
static u_int current_fiq[8] = { 0x3ff, 0x3ff, 0x3ff, 0x3ff, 0x3ff, 0x3ff, 0x3ff, 0x3ff }; static u_int current_fiq[8] = { 0x3ff, 0x3ff, 0x3ff, 0x3ff, 0x3ff, 0x3ff, 0x3ff, 0x3ff };
static bool update_fiq_targets(u_int cpu, bool enable, u_int triggered_fiq, bool resume_gicd) static bool update_fiq_targets(u_int cpu, bool enable, u_int triggered_fiq, bool resume_gicd)
@@ -560,16 +548,21 @@ static bool update_fiq_targets(u_int cpu, bool enable, u_int triggered_fiq, bool
static void suspend_resume_fiq(bool resume_gicc, bool resume_gicd) static void suspend_resume_fiq(bool resume_gicc, bool resume_gicd)
{ {
u_int cpu = read_mpidr() & 7; u_int cpu = arch_curr_cpu_num();
ASSERT(cpu < 8);
update_fiq_targets(cpu, resume_gicc, ~0, resume_gicd); update_fiq_targets(cpu, resume_gicc, ~0, resume_gicd);
} }
status_t sm_intc_fiq_enter(void) status_t sm_intc_fiq_enter(void)
{ {
u_int cpu = read_mpidr() & 7; u_int cpu = arch_curr_cpu_num();
u_int irq = GICREG(0, GICC_IAR) & 0x3ff; u_int irq = GICREG(0, GICC_IAR) & 0x3ff;
bool fiq_enabled; bool fiq_enabled;
ASSERT(cpu < 8);
LTRACEF("cpu %d, irq %i\n", cpu, irq); LTRACEF("cpu %d, irq %i\n", cpu, irq);
if (irq >= 1020) { if (irq >= 1020) {
@@ -597,7 +590,10 @@ status_t sm_intc_fiq_enter(void)
void sm_intc_fiq_exit(void) void sm_intc_fiq_exit(void)
{ {
u_int cpu = read_mpidr() & 7; u_int cpu = arch_curr_cpu_num();
ASSERT(cpu < 8);
LTRACEF("cpu %d, irq %i\n", cpu, current_fiq[cpu]); LTRACEF("cpu %d, irq %i\n", cpu, current_fiq[cpu]);
if (current_fiq[cpu] == 0x3ff) { if (current_fiq[cpu] == 0x3ff) {
dprintf(INFO, "%s: no fiq active, cpu %d\n", __func__, cpu); dprintf(INFO, "%s: no fiq active, cpu %d\n", __func__, cpu);