[platform][alterasoc] initial support for Altera Cyclone V based SoC

-Initial dev board is a Helio

platform/alterasoc/clocks.c

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2014 Travis Geiselbrecht
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <reg.h>
+#include <stdio.h>
+#include <reg.h>
+#include <kernel/thread.h>
+#include <platform/debug.h>
+#include <platform/alterasoc.h>
+#include <target/debugconfig.h>
+

platform/alterasoc/debug.c

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2008-2014 Travis Geiselbrecht
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <reg.h>
+#include <stdio.h>
+#include <kernel/thread.h>
+#include <dev/uart.h>
+#include <platform/debug.h>
+#include <target/debugconfig.h>
+#include <reg.h>
+
+void platform_dputc(char c)
+{
+    if (c == '\n')
+        uart_putc(DEBUG_UART, '\r');
+    uart_putc(DEBUG_UART, c);
+}
+
+int platform_dgetc(char *c, bool wait)
+{
+    int ret = uart_getc(DEBUG_UART, wait);
+    if (ret == -1)
+        return -1;
+    *c = ret;
+    return 0;
+}
+
+void platform_halt(void)
+{
+    arch_disable_ints();
+    for (;;);
+}

platform/alterasoc/include/platform/alterasoc.h

@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2014 Travis Geiselbrecht
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <reg.h>
+
+/* common addres space regions */
+#define FPGASLAVES_BASE   (0xc0000000)
+#define PERIPH_BASE       (0xfc000000)
+#define LWPFGASLAVES_BASE (0xff200000)
+
+/* hardware base addresses */
+#define STM_BASE            (0xfc000000)
+#define DAP_BASE            (0xff000000)
+#define EMAC0_BASE          (0xff700000)
+#define EMAC1_BASE          (0xff702000)
+#define SDMMC_BASE          (0xff704000)
+#define QSPI_BASE           (0xff705000)
+#define FPGAMGRREGS_BASE    (0xff706000)
+#define ACPIDMAP_BASE       (0xff707000)
+#define GPIO0_BASE          (0xff708000)
+#define GPIO1_BASE          (0xff709000)
+#define GPIO2_BASE          (0xff70a000)
+#define L3REGS_BASE         (0xff800000)
+#define NANDDATA_BASE       (0xff900000)
+#define QSPIDATA_BASE       (0xffa00000)
+#define USB0_BASE           (0xffb00000)
+#define USB1_BASE           (0xffb40000)
+#define NANDREGS_BASE       (0xffb80000)
+#define FPGAMGRDATA_BASE    (0xffb90000)
+#define CAN0_BASE           (0xffc00000)
+#define CAN1_BASE           (0xffc01000)
+#define UART0_BASE          (0xffc02000)
+#define UART1_BASE          (0xffc03000)
+#define I2C0_BASE           (0xffc04000)
+#define I2C1_BASE           (0xffc05000)
+#define I2C2_BASE           (0xffc06000)
+#define I2C3_BASE           (0xffc07000)
+#define SPTIMER0_BASE       (0xffc08000)
+#define SPTIMER1_BASE       (0xffc09000)
+#define SDRREGS_BASE        (0xffc20000)
+#define OSC1TIMER0_BASE     (0xffd00000)
+#define OSC1TIMER1_BASE     (0xffd01000)
+#define L4WD0_BASE          (0xffd02000)
+#define L4WD1_BASE          (0xffd03000)
+#define CLKMGR_BASE         (0xffd04000)
+#define RSTMGR_BASE         (0xffd05000)
+#define SYSMGR_BASE         (0xffd08000)
+#define DMANONSECURE_BASE   (0xffe00000)
+#define DMASECURE_BASE      (0xffe01000)
+#define SPIS0_BASE          (0xffe02000)
+#define SPIS1_BASE          (0xffe03000)
+#define SPIM0_BASE          (0xfff00000)
+#define SPIM1_BASE          (0xfff01000)
+#define SCANMGR_BASE        (0xfff02000)
+#define ROM_BASE            (0xfffd0000)
+#define MPUSCU_BASE         (0xfffec000)
+#define MPUL2_BASE          (0xfffef000)
+#define OCRAM_BASE          (0xffff0000)
+
+#define CPUPRIV_BASE        (MPUSCU_BASE)
+#define SCU_CONTROL_BASE    (CPUPRIV_BASE + 0x0000)
+#define GIC_PROC_BASE       (CPUPRIV_BASE + 0x0100)
+#define GLOBAL_TIMER_BASE   (CPUPRIV_BASE + 0x0200)
+#define PRIV_TIMER_BASE     (CPUPRIV_BASE + 0x0600)
+#define GIC_DISTRIB_BASE    (CPUPRIV_BASE + 0x1000)
+
+/* interrupts */
+#define CPU_GLOB_TIMER 27 // cortex-a9 specific timers
+#define CPU_PRIV_TIMER 29
+#define CPU_WATCHDOG   30
+
+#define FPGA_INT(n) (72 + (n))
+
+#define SPI0_INT        186
+#define SPI1_INT        187
+#define SPI2_INT        188
+#define SPI3_INT        189
+#define I2C0_INT        190
+#define I2C1_INT        191
+#define I2C2_INT        192
+#define I2C3_INT        193
+#define UART0_INT       194
+#define UART1_INT       195
+#define GPIO0_INT       196
+#define GPIO1_INT       197
+#define GPIO2_INT       198
+#define TIMER_L4SP0_INT 199
+#define TIMER_L4SP1_INT 200
+#define TIMER_OSC0_INT  201
+#define TIMER_OSC1_INT  202
+#define WDOG0_INT       203
+#define WDOG1_INT       204
+#define CLKMGR_INT      205
+#define MPUWAKEUP_INT   206
+#define FPGA_MAN_INT    207
+
+#define MAX_INT 212
+

platform/alterasoc/include/platform/gic.h

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2014 Travis Geiselbrecht
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <platform/alterasoc.h>
+
+#define GICBASE(n)  (CPUPRIV_BASE)
+#define GICC_OFFSET (0x0100)
+#define GICD_OFFSET (0x1000)
+

platform/alterasoc/platform.c

@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2012-2014 Travis Geiselbrecht
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <err.h>
+#include <debug.h>
+#include <trace.h>
+#include <dev/uart.h>
+#include <dev/interrupt/arm_gic.h>
+#include <platform.h>
+#include "platform_p.h"
+
+void platform_init_mmu_mappings(void)
+{
+}
+
+void platform_early_init(void)
+{
+    uart_init_early();
+
+    /* initialize the interrupt controller */
+    arm_gic_init();
+
+    /* initialize the timer block */
+    platform_init_timer(TIMER_CLOCK_FREQ);
+}
+
+void platform_init(void)
+{
+    uart_init();
+}
+

platform/alterasoc/platform_p.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2014 Travis Geiselbrecht
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <sys/types.h>
+
+void platform_init_timer(uint32_t freq);
+

platform/alterasoc/rules.mk

@@ -0,0 +1,32 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+MODULE := $(LOCAL_DIR)
+
+ARCH := arm
+ARM_CPU := cortex-a9
+
+MODULE_DEPS := \
+	lib/cbuf \
+	dev/interrupt/arm_gic
+
+GLOBAL_INCLUDES += \
+	$(LOCAL_DIR)/include
+
+MODULE_SRCS += \
+	$(LOCAL_DIR)/clocks.c \
+	$(LOCAL_DIR)/debug.c \
+	$(LOCAL_DIR)/platform.c \
+	$(LOCAL_DIR)/timer.c \
+	$(LOCAL_DIR)/uart.c
+
+MEMBASE := 0x0
+MEMSIZE ?= 0x10000000	# 256MB
+
+GLOBAL_DEFINES += \
+	MEMBASE=$(MEMBASE) \
+	MEMSIZE=$(MEMSIZE)
+
+LINKER_SCRIPT += \
+	$(BUILDDIR)/system-onesegment.ld
+
+include make/module.mk

platform/alterasoc/timer.c

@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2014 Travis Geiselbrecht
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <debug.h>
+#include <sys/types.h>
+#include <err.h>
+#include <stdio.h>
+#include <assert.h>
+#include <trace.h>
+#include <kernel/thread.h>
+#include <platform.h>
+#include <platform/interrupts.h>
+#include <platform/timer.h>
+#include <platform/alterasoc.h>
+#include "platform_p.h"
+
+/* driver for cortex-a9's private timer */
+#define LOCAL_TRACE 0
+
+#define TIMREG(reg)   (*REG32(PRIV_TIMER_BASE + (reg)))
+
+#define TIMER_LOAD      (0x00)
+#define TIMER_COUNTER   (0x04)
+#define TIMER_CONTROL   (0x08)
+#define TIMER_ISR       (0x0c)
+#define WDOG_LOAD       (0x20)
+#define WDOG_COUNTER    (0x24)
+#define WDOG_CONTROL    (0x28)
+#define WDOG_ISR        (0x2c)
+
+#define GTIMREG(reg)   (*REG32(GLOBAL_TIMER_BASE + (reg)))
+
+#define GTIMER_COUNT_LO (0x00)
+#define GTIMER_COUNT_HI (0x04)
+#define GTIMER_CONTROL  (0x08)
+#define GTIMER_ISR      (0x0c)
+#define GTIMER_COMPARE_LO (0x10)
+#define GTIMER_COMPARE_HI (0x14)
+#define GTIMER_INCREMENT (0x18)
+
+// XXX pull from someplace better
+#define TIMER_INPUT_CLOCK (200000000)
+
+static platform_timer_callback t_callback;
+
+static volatile uint ticks = 0;
+static lk_time_t periodic_interval;
+static uint32_t tick_freq;
+
+uint64_t get_global_val(void)
+{
+    uint32_t lo, hi;
+
+retry:
+    hi = GTIMREG(GTIMER_COUNT_HI);
+    lo = GTIMREG(GTIMER_COUNT_LO);
+    if (GTIMREG(GTIMER_COUNT_HI) != hi)
+        goto retry;
+
+
+    return ((uint64_t)hi << 32 | lo);
+}
+
+status_t platform_set_periodic_timer(platform_timer_callback callback, void *arg, lk_time_t interval)
+{
+    enter_critical_section();
+
+    LTRACEF("callback %p, arg %p, interval %lu\n", callback, arg, interval);
+
+    t_callback = callback;
+
+    periodic_interval = interval;
+
+    // disable timer
+    TIMREG(TIMER_CONTROL) = 0;
+
+    TIMREG(TIMER_LOAD) = (((uint64_t)TIMER_INPUT_CLOCK * interval) / 1000);
+    TIMREG(TIMER_CONTROL) = (1<<2) | (1<<1) | (1<<0); // irq enable, autoreload, enable
+
+    unmask_interrupt(CPU_PRIV_TIMER);
+
+    exit_critical_section();
+
+    return NO_ERROR;
+}
+
+lk_bigtime_t current_time_hires(void)
+{
+    lk_bigtime_t time;
+
+    time = ticks * periodic_interval * 1000ULL;
+
+    return time;
+}
+
+lk_time_t current_time(void)
+{
+    lk_time_t time;
+
+    time = ticks * periodic_interval;
+
+    return time;
+}
+
+static enum handler_return platform_tick(void *arg)
+{
+    ticks++;
+
+    LTRACE;
+
+    TIMREG(TIMER_ISR) = 1; // ack the irq
+
+    if (t_callback) {
+        return t_callback(arg, current_time());
+    } else {
+        return INT_NO_RESCHEDULE;
+    }
+}
+
+void platform_init_timer(uint32_t freq)
+{
+    /* disable timer */
+    TIMREG(TIMER_CONTROL) = 0;
+
+    /* kill the watchdog */
+    TIMREG(WDOG_CONTROL) = 0;
+
+    tick_freq = freq;
+
+    register_int_handler(CPU_PRIV_TIMER, &platform_tick, NULL);
+}
+
+/* vim: set ts=4 sw=4 expandtab: */

platform/alterasoc/uart.c

@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2014 Travis Geiselbrecht
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <reg.h>
+#include <bits.h>
+#include <stdio.h>
+#include <trace.h>
+#include <lib/cbuf.h>
+#include <kernel/thread.h>
+#include <platform/interrupts.h>
+#include <platform/debug.h>
+#include <platform/alterasoc.h>
+
+#define UART_THR (0x00)
+#define UART_RBR (0x00)
+#define UART_DLL (0x00)
+#define UART_IER (0x04)
+#define UART_DLH (0x04)
+#define UART_IIR (0x08)
+#define UART_FCR (0x08)
+#define UART_LCR (0x0c)
+#define UART_MCR (0x10)
+#define UART_LSR (0x14)
+#define UART_MSR (0x18)
+#define UART_SCR (0x1c)
+#define UART_USR (0x7c)
+#define UART_TFL (0x80)
+#define UART_RFL (0x84)
+#define UART_SRR (0x88)
+
+#define UARTREG(base, reg)  (*REG32((base)  + (reg)))
+
+#define RXBUF_SIZE 16
+
+static cbuf_t uart0_rx_buf;
+static cbuf_t uart1_rx_buf;
+
+static inline uintptr_t uart_to_ptr(unsigned int n) { return (n == 0) ? UART0_BASE : UART1_BASE; }
+static inline cbuf_t *uart_to_rxbuf(unsigned int n) { return (n == 0) ? &uart0_rx_buf : &uart1_rx_buf; }
+
+static enum handler_return uart_irq(void *arg)
+{
+    bool resched = false;
+    uint port = (uint)arg;
+    uintptr_t base = uart_to_ptr(port);
+
+    /* read interrupt identity */
+    uint32_t iir = UARTREG(base, UART_IIR);
+
+    /* receive data available */
+    if (BITS(iir, 3, 0) == 0x4) {
+        cbuf_t *rxbuf = uart_to_rxbuf(port);
+
+        /* while receive fifo not empty, read a char */
+        while ((UARTREG(base, UART_USR) & (1<<3))) {
+            char c = UARTREG(base, UART_RBR);
+            cbuf_write_char(rxbuf, c, false);
+
+            resched = true;
+        }
+    }
+
+    return resched ? INT_RESCHEDULE : INT_NO_RESCHEDULE;
+}
+
+void uart_init(void)
+{
+    cbuf_initialize(&uart0_rx_buf, RXBUF_SIZE);
+    cbuf_initialize(&uart1_rx_buf, RXBUF_SIZE);
+
+    register_int_handler(UART0_INT, &uart_irq, (void *)0);
+    register_int_handler(UART1_INT, &uart_irq, (void *)1);
+
+    // enable the fifo
+    UARTREG(uart_to_ptr(0), UART_FCR) = (1<<0); // enable rx fifo, set tx trigger to 0, set rx trigger to 0
+    UARTREG(uart_to_ptr(1), UART_FCR) = (1<<0); // enable rx fifo, set tx trigger to 0, set rx trigger to 0
+
+    // enable rx interrupt
+    UARTREG(uart_to_ptr(0), UART_IER) = (1<<0); // receive data interrupt
+    UARTREG(uart_to_ptr(1), UART_IER) = (1<<0); // receive data interrupt
+
+    unmask_interrupt(UART0_INT);
+    unmask_interrupt(UART1_INT);
+}
+
+void uart_init_early(void)
+{
+#if 0
+    UARTREG(uart_to_ptr(0), UART_CR) = (1<<4); // txen
+    UARTREG(uart_to_ptr(1), UART_CR) = (1<<4); // txen
+#endif
+}
+
+int uart_putc(int port, char c)
+{
+    uintptr_t base = uart_to_ptr(port);
+
+#if 1
+    /* spin while fifo is full */
+    while ((UARTREG(base, UART_USR) & (1<<1)) == 0)
+        ;
+#else
+    /* spin while fifo is not empty */
+    while ((UARTREG(base, UART_USR) & (1<<2)) == 0)
+        ;
+#endif
+    UARTREG(base, UART_THR) = c;
+
+    return 1;
+}
+
+int uart_getc(int port, bool wait)
+{
+#if 0
+    uintptr_t base = uart_to_ptr(port);
+
+    if ((UARTREG(base, UART_USR) & (1<<3)))
+        return UARTREG(base, UART_RBR);
+#else
+    cbuf_t *rxbuf = uart_to_rxbuf(port);
+
+    char c;
+    if (cbuf_read_char(rxbuf, &c, wait) == 1)
+        return c;
+#endif
+
+    return -1;
+}
+
+void uart_flush_tx(int port)
+{
+}
+
+void uart_flush_rx(int port)
+{
+}
+
+void uart_init_port(int port, uint baud)
+{
+}
+