[arch][riscv] Expose RISC-V mp kernel start

Support mp lk start on RISC-V. Several changes throughout were required:
- Add signal in asm start to force secondary harts to wait for bss to be
  cleared.
- Use mhartid in arch_curr_cpu_num, PLIC, and CLINT
- Use tp register as thread pointer instead of global variable.
- Support sending IPIs between harts using CLINT
- Add spinlock implementation

target/sifive-e/include/platform/sifive.h

@@ -25,3 +25,4 @@
 #define GPIO_REG_IOF_EN     14
 #define GPIO_REG_IOF_SEL    15
 
+#define PLIC_HART_IDX(hart)    0

target/sifive-unleashed/include/platform/sifive.h

@@ -20,3 +20,5 @@
 #define PWM0_BASE  0x10020000
 #define PWM1_BASE  0x10021000
 #define GPIO_BASE  0x10060000
+
+#define PLIC_HART_IDX(hart)    ((hart) ? ((2 * (hart)) - 1) : 0)

target/sifive-unleashed/rules.mk

@@ -4,6 +4,9 @@ MODULE := $(LOCAL_DIR)
 PLATFORM := sifive
 VARIANT := sifive_u
 
+WITH_SMP := 1
+SMP_MAX_CPUS := 5
+
 GLOBAL_DEFINES += SIFIVE_FREQ=500000000 # 500 MHz
 
 MEMBASE ?= 0x080000000