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[platform][stm32f4xx] based on stm32f2xx platform

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Quick first pass at stm32f4xx support using the latest STM32F4
peripheral library code.  Probably could (and should) share more
with stm32fxxx.
This commit is contained in:
Brian Swetland
2015-06-19 18:47:02 -07:00
parent 3644293ed7
commit acf7a49c4f
12 changed files with 1012 additions and 0 deletions
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4
platform/stm32f4xx/CMSIS/rules.mk Normal file
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LOCAL_DIR := $(GET_LOCAL_DIR)
GLOBAL_INCLUDES += $(LOCAL_DIR)

45
platform/stm32f4xx/STM32F4xx_StdPeriph_Driver/rules.mk Normal file
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LOCAL_DIR := $(GET_LOCAL_DIR)
GLOBAL_INCLUDES += $(LOCAL_DIR)/inc
MODULE_SRCS += \
$(LOCAL_DIR)/src/misc.c \
$(LOCAL_DIR)/src/stm32f4xx_adc.c \
$(LOCAL_DIR)/src/stm32f4xx_can.c \
$(LOCAL_DIR)/src/stm32f4xx_cec.c \
$(LOCAL_DIR)/src/stm32f4xx_crc.c \
$(LOCAL_DIR)/src/stm32f4xx_cryp_aes.c \
$(LOCAL_DIR)/src/stm32f4xx_cryp.c \
$(LOCAL_DIR)/src/stm32f4xx_cryp_des.c \
$(LOCAL_DIR)/src/stm32f4xx_cryp_tdes.c \
$(LOCAL_DIR)/src/stm32f4xx_dac.c \
$(LOCAL_DIR)/src/stm32f4xx_dbgmcu.c \
$(LOCAL_DIR)/src/stm32f4xx_dcmi.c \
$(LOCAL_DIR)/src/stm32f4xx_dma2d.c \
$(LOCAL_DIR)/src/stm32f4xx_dma.c \
$(LOCAL_DIR)/src/stm32f4xx_exti.c \
$(LOCAL_DIR)/src/stm32f4xx_flash.c \
$(LOCAL_DIR)/src/stm32f4xx_flash_ramfunc.c \
$(LOCAL_DIR)/src/stm32f4xx_fmpi2c.c \
$(LOCAL_DIR)/src/stm32f4xx_fsmc.c \
$(LOCAL_DIR)/src/stm32f4xx_gpio.c \
$(LOCAL_DIR)/src/stm32f4xx_hash.c \
$(LOCAL_DIR)/src/stm32f4xx_hash_md5.c \
$(LOCAL_DIR)/src/stm32f4xx_hash_sha1.c \
$(LOCAL_DIR)/src/stm32f4xx_i2c.c \
$(LOCAL_DIR)/src/stm32f4xx_iwdg.c \
$(LOCAL_DIR)/src/stm32f4xx_ltdc.c \
$(LOCAL_DIR)/src/stm32f4xx_pwr.c \
$(LOCAL_DIR)/src/stm32f4xx_qspi.c \
$(LOCAL_DIR)/src/stm32f4xx_rcc.c \
$(LOCAL_DIR)/src/stm32f4xx_rng.c \
$(LOCAL_DIR)/src/stm32f4xx_rtc.c \
$(LOCAL_DIR)/src/stm32f4xx_sai.c \
$(LOCAL_DIR)/src/stm32f4xx_sdio.c \
$(LOCAL_DIR)/src/stm32f4xx_spdifrx.c \
$(LOCAL_DIR)/src/stm32f4xx_spi.c \
$(LOCAL_DIR)/src/stm32f4xx_syscfg.c \
$(LOCAL_DIR)/src/stm32f4xx_tim.c \
$(LOCAL_DIR)/src/stm32f4xx_usart.c \
$(LOCAL_DIR)/src/stm32f4xx_wwdg.c \
$(LOCAL_DIR)/src/system_stm32f4xx.c

62
platform/stm32f4xx/debug.c Normal file
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/*
* Copyright (c) 2012 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <stdarg.h>
#include <reg.h>
#include <debug.h>
#include <stdio.h>
#include <kernel/thread.h>
#include <platform/debug.h>
#include <arch/ops.h>
#include <dev/uart.h>
#include <target/debugconfig.h>
#include <stm32f4xx_rcc.h>
#include <stm32f4xx_usart.h>
#include <arch/arm/cm.h>
void stm32_debug_early_init(void)
{
uart_init_early();
}
/* later in the init process */
void stm32_debug_init(void)
{
uart_init();
}
void platform_dputc(char c)
{
if (c == '\n')
uart_putc(DEBUG_UART, '\r');
uart_putc(DEBUG_UART, c);
}
int platform_dgetc(char *c, bool wait)
{
int ret = uart_getc(DEBUG_UART, wait);
if (ret == -1)
return -1;
*c = ret;
return 0;
}

116
platform/stm32f4xx/gpio.c Normal file
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/*
* Copyright (c) 2012 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <debug.h>
#include <assert.h>
#include <dev/gpio.h>
#include <platform/stm32.h>
#include <platform/gpio.h>
#include <stm32f4xx_gpio.h>
#include <stm32f4xx_rcc.h>
static GPIO_TypeDef *port_to_pointer(unsigned int port)
{
switch (port) {
default:
case GPIO_PORT_A:
return GPIOA;
case GPIO_PORT_B:
return GPIOB;
case GPIO_PORT_C:
return GPIOC;
case GPIO_PORT_D:
return GPIOD;
case GPIO_PORT_E:
return GPIOE;
case GPIO_PORT_F:
return GPIOF;
case GPIO_PORT_G:
return GPIOG;
case GPIO_PORT_H:
return GPIOH;
case GPIO_PORT_I:
return GPIOI;
}
}
static void enable_port(unsigned int port)
{
DEBUG_ASSERT(port <= GPIO_PORT_I);
/* happens to be the RCC ids are sequential bits, so we can start from A and shift */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA << port, ENABLE);
}
void stm32_gpio_early_init(void)
{
}
int gpio_config(unsigned nr, unsigned flags)
{
uint port = GPIO_PORT(nr);
uint pin = GPIO_PIN(nr);
enable_port(port);
GPIO_InitTypeDef init;
init.GPIO_Speed = GPIO_Speed_50MHz;
init.GPIO_Pin = (1 << pin);
init.GPIO_PuPd = GPIO_PuPd_NOPULL;
if (flags & GPIO_INPUT) {
init.GPIO_Mode = GPIO_Mode_IN;
} else if (flags & GPIO_OUTPUT) {
init.GPIO_Mode = GPIO_Mode_OUT;
} else if (flags & GPIO_STM32_AF) {
init.GPIO_Mode = GPIO_Mode_AF;
GPIO_PinAFConfig(port_to_pointer(port), pin, GPIO_AFNUM(flags));
}
if (flags & GPIO_PULLUP) {
init.GPIO_PuPd = GPIO_PuPd_UP;
} else if (flags & GPIO_PULLDOWN) {
init.GPIO_PuPd = GPIO_PuPd_DOWN;
}
if (flags & GPIO_STM32_OD) {
init.GPIO_OType = GPIO_OType_OD;
} else {
init.GPIO_OType = GPIO_OType_PP;
}
GPIO_Init(port_to_pointer(port), &init);
return 0;
}
void gpio_set(unsigned nr, unsigned on)
{
GPIO_WriteBit(port_to_pointer(GPIO_PORT(nr)), 1 << GPIO_PIN(nr), on);
}
int gpio_get(unsigned nr)
{
return GPIO_ReadInputDataBit(port_to_pointer(GPIO_PORT(nr)), 1 << GPIO_PIN(nr));
}

29
platform/stm32f4xx/include/platform/gpio.h Normal file
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#ifndef __PLATFORM_STM32_GPIO_H
#define __PLATFORM_STM32_GPIO_H
/* helper defines for STM32 platforms */
/* flag to gpio_configure */
#define GPIO_STM32_AF (0x1 << 16)
#define GPIO_STM32_OD (0x2 << 16)
#define GPIO_STM32_AFn(n) ((n) << 24)
/* gpio port/pin is packed into a single unsigned int in 16x:8port:8pin format */
#define GPIO(port, pin) ((unsigned int)(((port) << 8) | (pin)))
#define GPIO_PORT(gpio) (((gpio) >> 8) & 0xff)
#define GPIO_PIN(gpio) ((gpio) & 0xff)
#define GPIO_AFNUM(gpio) (((gpio) >> 24) & 0xf)
#define GPIO_PORT_A 0
#define GPIO_PORT_B 1
#define GPIO_PORT_C 2
#define GPIO_PORT_D 3
#define GPIO_PORT_E 4
#define GPIO_PORT_F 5
#define GPIO_PORT_G 6
#define GPIO_PORT_H 7
#define GPIO_PORT_I 8
#endif

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platform/stm32f4xx/include/platform/platform_cm.h Normal file
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/*
* Copyright (c) 2012 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __PLATFORM_CM_H
#define __PLATFORM_CM_H
#include <stm32f4xx.h>
#endif

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platform/stm32f4xx/include/platform/stm32.h Normal file
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/*
* Copyright (c) 2012 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __PLATFORM_STM32_H
#define __PLATFORM_STM32_H
void stm32_debug_early_init(void);
void stm32_debug_init(void);
void stm32_timer_early_init(void);
void stm32_timer_init(void);
void stm32_gpio_early_init(void);
void stm32_flash_nor_early_init(void);
void stm32_flash_nor_init(void);
#endif

49
platform/stm32f4xx/init.c Normal file
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/*
* Copyright (c) 2012 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <err.h>
#include <debug.h>
#include <dev/uart.h>
#include <platform.h>
#include <platform/stm32.h>
#include <arch/arm/cm.h>
#include <stm32f4xx_rcc.h>
#include "system_stm32f4xx.h"
void platform_early_init(void)
{
// Crank up the clock before initing timers.
SystemInit();
// start the systick timer
RCC_ClocksTypeDef clocks;
RCC_GetClocksFreq(&clocks);
arm_cm_systick_init(clocks.SYSCLK_Frequency);
stm32_timer_early_init();
stm32_gpio_early_init();
}
void platform_init(void)
{
stm32_timer_init();
}

57
platform/stm32f4xx/rules.mk Normal file
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LOCAL_DIR := $(GET_LOCAL_DIR)
MODULE := $(LOCAL_DIR)
# ROMBASE, MEMBASE, and MEMSIZE are required for the linker script
ROMBASE := 0x08000000
MEMBASE := 0x20000000
# default memsize, specific STM32_CHIP may override this
# and target/project may have already overridden
MEMSIZE ?= 131072
ARCH := arm
ARM_CPU := cortex-m4
# TODO: integrate better with platform/stm32f4xx/CMSIS/stm32f4xx.h
ifeq ($(STM32_CHIP),stm32f407)
GLOBAL_DEFINES += STM32F40_41xxx
FOUND_CHIP := true
endif
ifeq ($(STM32_CHIP),stm32f417)
FOUND_CHIP := true
GLOBAL_DEFINES += STM32F40_41xxx
endif
ifeq ($(FOUND_CHIP),)
$(error unknown STM32F4xx chip $(STM32_CHIP))
endif
GLOBAL_DEFINES += \
MEMSIZE=$(MEMSIZE)
GLOBAL_INCLUDES += \
$(LOCAL_DIR)/include
MODULE_SRCS += \
$(LOCAL_DIR)/init.c \
$(LOCAL_DIR)/vectab.c \
$(LOCAL_DIR)/gpio.c \
$(LOCAL_DIR)/timer.c \
$(LOCAL_DIR)/debug.c \
$(LOCAL_DIR)/uart.c
# use a two segment memory layout, where all of the read-only sections
# of the binary reside in rom, and the read/write are in memory. The
# ROMBASE, MEMBASE, and MEMSIZE make variables are required to be set
# for the linker script to be generated properly.
#
LINKER_SCRIPT += \
$(BUILDDIR)/system-twosegment.ld
MODULE_DEPS += \
arch/arm/arm-m/systick \
lib/cbuf
include $(LOCAL_DIR)/STM32F4xx_StdPeriph_Driver/rules.mk $(LOCAL_DIR)/CMSIS/rules.mk
include make/module.mk

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platform/stm32f4xx/timer.c Normal file
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/*
* Copyright (c) 2012 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <debug.h>
#include <trace.h>
#include <err.h>
#include <sys/types.h>
#include <kernel/thread.h>
#include <platform.h>
#include <platform/timer.h>
#include <stm32f4xx_rcc.h>
#include <stm32f4xx_tim.h>
#include <misc.h>
#include <arch/arm/cm.h>
#define LOCAL_TRACE 0
static void stm32_tim_irq(uint num)
{
TRACEF("tim irq %d\n", num);
PANIC_UNIMPLEMENTED;
}
void stm32_TIM3_IRQ(void)
{
stm32_tim_irq(3);
}
void stm32_TIM4_IRQ(void)
{
stm32_tim_irq(4);
}
void stm32_TIM5_IRQ(void)
{
stm32_tim_irq(5);
}
void stm32_TIM6_IRQ(void)
{
stm32_tim_irq(6);
}
void stm32_TIM7_IRQ(void)
{
stm32_tim_irq(7);
}
/* time base */
void stm32_TIM2_IRQ(void)
{
stm32_tim_irq(2);
}
void stm32_timer_early_init(void)
{
}
void stm32_timer_init(void)
{
}

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platform/stm32f4xx/uart.c Normal file
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/*
* Copyright (c) 2012 Kent Ryhorchuk
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <stdarg.h>
#include <reg.h>
#include <debug.h>
#include <stdio.h>
#include <assert.h>
#include <lib/cbuf.h>
#include <kernel/thread.h>
#include <platform/debug.h>
#include <arch/ops.h>
#include <dev/uart.h>
#include <target/debugconfig.h>
#include <stm32f4xx_rcc.h>
#include <stm32f4xx_usart.h>
#include <arch/arm/cm.h>
#define RXBUF_SIZE 16
#ifdef ENABLE_UART1
cbuf_t uart1_rx_buf;
#ifndef UART1_FLOWCONTROL
#define UART1_FLOWCONTROL USART_HardwareFlowControl_None
#endif
#endif
#ifdef ENABLE_UART2
cbuf_t uart2_rx_buf;
#ifndef UART2_FLOWCONTROL
#define UART2_FLOWCONTROL USART_HardwareFlowControl_None
#endif
#endif
#ifdef ENABLE_UART3
cbuf_t uart3_rx_buf;
#ifndef UART3_FLOWCONTROL
#define UART3_FLOWCONTROL USART_HardwareFlowControl_None
#endif
#endif
#ifdef ENABLE_UART6
cbuf_t uart6_rx_buf;
#ifndef UART6_FLOWCONTROL
#define UART6_FLOWCONTROL USART_HardwareFlowControl_None
#endif
#endif
#ifdef ENABLE_UART1
#endif
#ifdef ENABLE_UART2
#endif
#ifdef ENABLE_UART3
#endif
static void usart_init1_early(USART_TypeDef *usart, uint16_t flowcontrol, int irqn)
{
USART_InitTypeDef init;
init.USART_BaudRate = 115200;
init.USART_WordLength = USART_WordLength_8b;
init.USART_StopBits = USART_StopBits_1;
init.USART_Parity = USART_Parity_No;
init.USART_Mode = USART_Mode_Tx|USART_Mode_Rx;
init.USART_HardwareFlowControl = flowcontrol;
USART_Init(usart, &init);
USART_ITConfig(usart, USART_IT_RXNE, DISABLE);
NVIC_DisableIRQ(irqn);
USART_Cmd(usart, ENABLE);
}
static void usart_init1(USART_TypeDef *usart, int irqn, cbuf_t *rxbuf)
{
cbuf_initialize(rxbuf, RXBUF_SIZE);
USART_ITConfig(usart, USART_IT_RXNE, ENABLE);
NVIC_EnableIRQ(irqn);
USART_Cmd(usart, ENABLE);
}
void uart_init_early(void)
{
#ifdef ENABLE_UART1
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
#endif
#ifdef ENABLE_UART2
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
#endif
#ifdef ENABLE_UART3
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
#endif
#ifdef ENABLE_UART6
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE);
#endif
#ifdef ENABLE_UART1
usart_init1_early(USART1, UART1_FLOWCONTROL, USART1_IRQn);
#endif
#ifdef ENABLE_UART2
usart_init1_early(USART2, UART2_FLOWCONTROL, USART2_IRQn);
#endif
#ifdef ENABLE_UART3
usart_init1_early(USART3, UART3_FLOWCONTROL, USART3_IRQn);
#endif
#ifdef ENABLE_UART6
usart_init1_early(USART6, UART6_FLOWCONTROL, USART6_IRQn);
#endif
}
void uart_init(void)
{
#ifdef ENABLE_UART1
usart_init1(USART1, USART1_IRQn, &uart1_rx_buf);
#endif
#ifdef ENABLE_UART2
usart_init1(USART2, USART2_IRQn, &uart2_rx_buf);
#endif
#ifdef ENABLE_UART3
usart_init1(USART3, USART3_IRQn, &uart3_rx_buf);
#endif
#ifdef ENABLE_UART6
usart_init1(USART6, USART6_IRQn, &uart6_rx_buf);
#endif
}
void uart_rx_irq(USART_TypeDef *usart, cbuf_t *rxbuf)
{
arm_cm_irq_entry();
bool resched = false;
while (USART_GetFlagStatus(usart, USART_FLAG_RXNE)) {
if (!cbuf_space_avail(rxbuf)) {
// Overflow - let flow control do its thing by not
// reading the from the FIFO.
USART_ITConfig(usart, USART_IT_RXNE, DISABLE);
break;
}
char c = USART_ReceiveData(usart);
cbuf_write_char(rxbuf, c, false);
resched = true;
}
arm_cm_irq_exit(resched);
}
#ifdef ENABLE_UART1
void stm32_USART1_IRQ(void)
{
uart_rx_irq(USART1, &uart1_rx_buf);
}
#endif
#ifdef ENABLE_UART2
void stm32_USART2_IRQ(void)
{
uart_rx_irq(USART2, &uart2_rx_buf);
}
#endif
#ifdef ENABLE_UART3
void stm32_USART3_IRQ(void)
{
uart_rx_irq(USART3, &uart3_rx_buf);
}
#endif
#ifdef ENABLE_UART6
void stm32_USART6_IRQ(void)
{
uart_rx_irq(USART6, &uart6_rx_buf);
}
#endif
static void usart_putc(USART_TypeDef *usart, char c)
{
while (USART_GetFlagStatus(usart, USART_FLAG_TXE) == 0);
USART_SendData(usart, c);
while (USART_GetFlagStatus(usart, USART_FLAG_TC) == 0);
}
static int usart_getc(USART_TypeDef *usart, cbuf_t *rxbuf, bool wait)
{
char c;
cbuf_read_char(rxbuf, &c, wait);
if (cbuf_space_avail(rxbuf) > RXBUF_SIZE/2)
USART_ITConfig(usart, USART_IT_RXNE, ENABLE);
return c;
}
static USART_TypeDef *get_usart(int port)
{
switch (port) {
#ifdef ENABLE_UART1
case 1:
return USART1;
#endif
#ifdef ENABLE_UART2
case 2:
return USART2;
#endif
#ifdef ENABLE_UART3
case 3:
return USART3;
#endif
#ifdef ENABLE_UART6
case 6:
return USART6;
#endif
default:
ASSERT(false);
return 0;
}
}
static cbuf_t *get_rxbuf(int port)
{
switch (port) {
#ifdef ENABLE_UART1
case 1:
return &uart1_rx_buf;
#endif
#ifdef ENABLE_UART2
case 2:
return &uart2_rx_buf;
#endif
#ifdef ENABLE_UART3
case 3:
return &uart3_rx_buf;
#endif
#ifdef ENABLE_UART6
case 6:
return &uart6_rx_buf;
#endif
default:
ASSERT(false);
return 0;
}
}
int uart_putc(int port, char c)
{
USART_TypeDef *usart = get_usart(port);
usart_putc(usart, c);
return 1;
}
int uart_getc(int port, bool wait)
{
cbuf_t *rxbuf = get_rxbuf(port);
USART_TypeDef *usart = get_usart(port);
return usart_getc(usart, rxbuf, wait);
}
void uart_flush_tx(int port) {}
void uart_flush_rx(int port) {}
void uart_init_port(int port, uint baud)
{
// TODO - later
PANIC_UNIMPLEMENTED;
}

220
platform/stm32f4xx/vectab.c Normal file
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@@ -0,0 +1,220 @@
/*
* Copyright (c) 2012 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <debug.h>
#include <compiler.h>
#include <stm32f4xx.h>
#include <arch/arm/cm.h>
#include <platform/stm32.h>
#include <target/debugconfig.h>
#include <lib/cbuf.h>
/* un-overridden irq handler */
void stm32_dummy_irq(void)
{
arm_cm_irq_entry();
panic("unhandled irq\n");
}
/* a list of default handlers that are simply aliases to the dummy handler */
#define DEFAULT_HANDLER(x) \
void stm32_##x(void) __WEAK_ALIAS("stm32_dummy_irq");
DEFAULT_HANDLER(WWDG_IRQ);
DEFAULT_HANDLER(PVD_IRQ);
DEFAULT_HANDLER(TAMP_STAMP_IRQ);
DEFAULT_HANDLER(RTC_WKUP_IRQ);
DEFAULT_HANDLER(FLASH_IRQ);
DEFAULT_HANDLER(RCC_IRQ);
DEFAULT_HANDLER(EXTI0_IRQ);
DEFAULT_HANDLER(EXTI1_IRQ);
DEFAULT_HANDLER(EXTI2_IRQ);
DEFAULT_HANDLER(EXTI3_IRQ);
DEFAULT_HANDLER(EXTI4_IRQ);
DEFAULT_HANDLER(DMA1_Stream0_IRQ);
DEFAULT_HANDLER(DMA1_Stream1_IRQ);
DEFAULT_HANDLER(DMA1_Stream2_IRQ);
DEFAULT_HANDLER(DMA1_Stream3_IRQ);
DEFAULT_HANDLER(DMA1_Stream4_IRQ);
DEFAULT_HANDLER(DMA1_Stream5_IRQ);
DEFAULT_HANDLER(DMA1_Stream6_IRQ);
DEFAULT_HANDLER(ADC_IRQ);
DEFAULT_HANDLER(CAN1_TX_IRQ);
DEFAULT_HANDLER(CAN1_RX0_IRQ);
DEFAULT_HANDLER(CAN1_RX1_IRQ);
DEFAULT_HANDLER(CAN1_SCE_IRQ);
DEFAULT_HANDLER(EXTI9_5_IRQ);
DEFAULT_HANDLER(TIM1_BRK_TIM9_IRQ);
DEFAULT_HANDLER(TIM1_UP_TIM10_IRQ);
DEFAULT_HANDLER(TIM1_TRG_COM_TIM11_IRQ);
DEFAULT_HANDLER(TIM1_CC_IRQ);
DEFAULT_HANDLER(TIM2_IRQ);
DEFAULT_HANDLER(TIM3_IRQ);
DEFAULT_HANDLER(TIM4_IRQ);
DEFAULT_HANDLER(I2C1_EV_IRQ);
DEFAULT_HANDLER(I2C1_ER_IRQ);
DEFAULT_HANDLER(I2C2_EV_IRQ);
DEFAULT_HANDLER(I2C2_ER_IRQ);
DEFAULT_HANDLER(SPI1_IRQ);
DEFAULT_HANDLER(SPI2_IRQ);
DEFAULT_HANDLER(USART1_IRQ);
DEFAULT_HANDLER(USART2_IRQ);
DEFAULT_HANDLER(USART3_IRQ);
DEFAULT_HANDLER(EXTI15_10_IRQ);
DEFAULT_HANDLER(RTC_Alarm_IRQ);
DEFAULT_HANDLER(OTG_FS_WKUP_IRQ);
DEFAULT_HANDLER(TIM8_BRK_TIM12_IRQ);
DEFAULT_HANDLER(TIM8_UP_TIM13_IRQ);
DEFAULT_HANDLER(TIM8_TRG_COM_TIM14_IRQ);
DEFAULT_HANDLER(TIM8_CC_IRQ);
DEFAULT_HANDLER(DMA1_Stream7_IRQ);
DEFAULT_HANDLER(FSMC_IRQ);
DEFAULT_HANDLER(SDIO_IRQ);
DEFAULT_HANDLER(TIM5_IRQ);
DEFAULT_HANDLER(SPI3_IRQ);
DEFAULT_HANDLER(UART4_IRQ);
DEFAULT_HANDLER(UART5_IRQ);
DEFAULT_HANDLER(TIM6_DAC_IRQ);
DEFAULT_HANDLER(TIM7_IRQ);
DEFAULT_HANDLER(DMA2_Stream0_IRQ);
DEFAULT_HANDLER(DMA2_Stream1_IRQ);
DEFAULT_HANDLER(DMA2_Stream2_IRQ);
DEFAULT_HANDLER(DMA2_Stream3_IRQ);
DEFAULT_HANDLER(DMA2_Stream4_IRQ);
DEFAULT_HANDLER(ETH_IRQ);
DEFAULT_HANDLER(ETH_WKUP_IRQ);
DEFAULT_HANDLER(CAN2_TX_IRQ);
DEFAULT_HANDLER(CAN2_RX0_IRQ);
DEFAULT_HANDLER(CAN2_RX1_IRQ);
DEFAULT_HANDLER(CAN2_SCE_IRQ);
DEFAULT_HANDLER(OTG_FS_IRQ);
DEFAULT_HANDLER(DMA2_Stream5_IRQ);
DEFAULT_HANDLER(DMA2_Stream6_IRQ);
DEFAULT_HANDLER(DMA2_Stream7_IRQ);
DEFAULT_HANDLER(USART6_IRQ);
DEFAULT_HANDLER(I2C3_EV_IRQ);
DEFAULT_HANDLER(I2C3_ER_IRQ);
DEFAULT_HANDLER(OTG_HS_EP1_OUT_IRQ);
DEFAULT_HANDLER(OTG_HS_EP1_IN_IRQ);
DEFAULT_HANDLER(OTG_HS_WKUP_IRQ);
DEFAULT_HANDLER(OTG_HS_IRQ);
DEFAULT_HANDLER(DCMI_IRQ);
DEFAULT_HANDLER(CRYP_IRQ);
DEFAULT_HANDLER(HASH_RNG_IRQ);
#define VECTAB_ENTRY(x) [x##n] = stm32_##x
/* appended to the end of the main vector table */
const void * const __SECTION(".text.boot.vectab2") vectab2[] = {
VECTAB_ENTRY(WWDG_IRQ), /* Window WatchDog Interrupt */
VECTAB_ENTRY(PVD_IRQ), /* PVD through EXTI Line detection Interrupt */
VECTAB_ENTRY(TAMP_STAMP_IRQ), /* Tamper and TimeStamp interrupts through the EXTI line */
VECTAB_ENTRY(RTC_WKUP_IRQ), /* RTC Wakeup interrupt through the EXTI line */
VECTAB_ENTRY(FLASH_IRQ), /* FLASH global Interrupt */
VECTAB_ENTRY(RCC_IRQ), /* RCC global Interrupt */
VECTAB_ENTRY(EXTI0_IRQ), /* EXTI Line0 Interrupt */
VECTAB_ENTRY(EXTI1_IRQ), /* EXTI Line1 Interrupt */
VECTAB_ENTRY(EXTI2_IRQ), /* EXTI Line2 Interrupt */
VECTAB_ENTRY(EXTI3_IRQ), /* EXTI Line3 Interrupt */
VECTAB_ENTRY(EXTI4_IRQ), /* EXTI Line4 Interrupt */
VECTAB_ENTRY(DMA1_Stream0_IRQ), /* DMA1 Stream 0 global Interrupt */
VECTAB_ENTRY(DMA1_Stream1_IRQ), /* DMA1 Stream 1 global Interrupt */
VECTAB_ENTRY(DMA1_Stream2_IRQ), /* DMA1 Stream 2 global Interrupt */
VECTAB_ENTRY(DMA1_Stream3_IRQ), /* DMA1 Stream 3 global Interrupt */
VECTAB_ENTRY(DMA1_Stream4_IRQ), /* DMA1 Stream 4 global Interrupt */
VECTAB_ENTRY(DMA1_Stream5_IRQ), /* DMA1 Stream 5 global Interrupt */
VECTAB_ENTRY(DMA1_Stream6_IRQ), /* DMA1 Stream 6 global Interrupt */
VECTAB_ENTRY(ADC_IRQ), /* ADC1, ADC2 and ADC3 global Interrupts */
VECTAB_ENTRY(CAN1_TX_IRQ), /* CAN1 TX Interrupt */
VECTAB_ENTRY(CAN1_RX0_IRQ), /* CAN1 RX0 Interrupt */
VECTAB_ENTRY(CAN1_RX1_IRQ), /* CAN1 RX1 Interrupt */
VECTAB_ENTRY(CAN1_SCE_IRQ), /* CAN1 SCE Interrupt */
VECTAB_ENTRY(EXTI9_5_IRQ), /* External Line[9:5] Interrupts */
VECTAB_ENTRY(TIM1_BRK_TIM9_IRQ), /* TIM1 Break interrupt and TIM9 global interrupt */
VECTAB_ENTRY(TIM1_UP_TIM10_IRQ), /* TIM1 Update Interrupt and TIM10 global interrupt */
VECTAB_ENTRY(TIM1_TRG_COM_TIM11_IRQ), /* TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
VECTAB_ENTRY(TIM1_CC_IRQ), /* TIM1 Capture Compare Interrupt */
VECTAB_ENTRY(TIM2_IRQ), /* TIM2 global Interrupt */
VECTAB_ENTRY(TIM3_IRQ), /* TIM3 global Interrupt */
VECTAB_ENTRY(TIM4_IRQ), /* TIM4 global Interrupt */
VECTAB_ENTRY(I2C1_EV_IRQ), /* I2C1 Event Interrupt */
VECTAB_ENTRY(I2C1_ER_IRQ), /* I2C1 Error Interrupt */
VECTAB_ENTRY(I2C2_EV_IRQ), /* I2C2 Event Interrupt */
VECTAB_ENTRY(I2C2_ER_IRQ), /* I2C2 Error Interrupt */
VECTAB_ENTRY(SPI1_IRQ), /* SPI1 global Interrupt */
VECTAB_ENTRY(SPI2_IRQ), /* SPI2 global Interrupt */
VECTAB_ENTRY(USART1_IRQ), /* USART1 global Interrupt */
VECTAB_ENTRY(USART2_IRQ), /* USART2 global Interrupt */
VECTAB_ENTRY(USART3_IRQ), /* USART3 global Interrupt */
VECTAB_ENTRY(EXTI15_10_IRQ), /* External Line[15:10] Interrupts */
VECTAB_ENTRY(RTC_Alarm_IRQ), /* RTC Alarm (A and B) through EXTI Line Interrupt */
VECTAB_ENTRY(OTG_FS_WKUP_IRQ), /* USB OTG FS Wakeup through EXTI line interrupt */
VECTAB_ENTRY(TIM8_BRK_TIM12_IRQ), /* TIM8 Break Interrupt and TIM12 global interrupt */
VECTAB_ENTRY(TIM8_UP_TIM13_IRQ), /* TIM8 Update Interrupt and TIM13 global interrupt */
VECTAB_ENTRY(TIM8_TRG_COM_TIM14_IRQ), /* TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
VECTAB_ENTRY(TIM8_CC_IRQ), /* TIM8 Capture Compare Interrupt */
VECTAB_ENTRY(DMA1_Stream7_IRQ), /* DMA1 Stream7 Interrupt */
VECTAB_ENTRY(FSMC_IRQ), /* FSMC global Interrupt */
VECTAB_ENTRY(SDIO_IRQ), /* SDIO global Interrupt */
VECTAB_ENTRY(TIM5_IRQ), /* TIM5 global Interrupt */
VECTAB_ENTRY(SPI3_IRQ), /* SPI3 global Interrupt */
VECTAB_ENTRY(UART4_IRQ), /* UART4 global Interrupt */
VECTAB_ENTRY(UART5_IRQ), /* UART5 global Interrupt */
VECTAB_ENTRY(TIM6_DAC_IRQ), /* TIM6 global and DAC1&2 underrun error interrupts */
VECTAB_ENTRY(TIM7_IRQ), /* TIM7 global interrupt */
VECTAB_ENTRY(DMA2_Stream0_IRQ), /* DMA2 Stream 0 global Interrupt */
VECTAB_ENTRY(DMA2_Stream1_IRQ), /* DMA2 Stream 1 global Interrupt */
VECTAB_ENTRY(DMA2_Stream2_IRQ), /* DMA2 Stream 2 global Interrupt */
VECTAB_ENTRY(DMA2_Stream3_IRQ), /* DMA2 Stream 3 global Interrupt */
VECTAB_ENTRY(DMA2_Stream4_IRQ), /* DMA2 Stream 4 global Interrupt */
VECTAB_ENTRY(ETH_IRQ), /* Ethernet global Interrupt */
VECTAB_ENTRY(ETH_WKUP_IRQ), /* Ethernet Wakeup through EXTI line Interrupt */
VECTAB_ENTRY(CAN2_TX_IRQ), /* CAN2 TX Interrupt */
VECTAB_ENTRY(CAN2_RX0_IRQ), /* CAN2 RX0 Interrupt */
VECTAB_ENTRY(CAN2_RX1_IRQ), /* CAN2 RX1 Interrupt */
VECTAB_ENTRY(CAN2_SCE_IRQ), /* CAN2 SCE Interrupt */
VECTAB_ENTRY(OTG_FS_IRQ), /* USB OTG FS global Interrupt */
VECTAB_ENTRY(DMA2_Stream5_IRQ), /* DMA2 Stream 5 global interrupt */
VECTAB_ENTRY(DMA2_Stream6_IRQ), /* DMA2 Stream 6 global interrupt */
VECTAB_ENTRY(DMA2_Stream7_IRQ), /* DMA2 Stream 7 global interrupt */
VECTAB_ENTRY(USART6_IRQ), /* USART6 global interrupt */
VECTAB_ENTRY(I2C3_EV_IRQ), /* I2C3 event interrupt */
VECTAB_ENTRY(I2C3_ER_IRQ), /* I2C3 error interrupt */
VECTAB_ENTRY(OTG_HS_EP1_OUT_IRQ), /* USB OTG HS End Point 1 Out global interrupt */
VECTAB_ENTRY(OTG_HS_EP1_IN_IRQ), /* USB OTG HS End Point 1 In global interrupt */
VECTAB_ENTRY(OTG_HS_WKUP_IRQ), /* USB OTG HS Wakeup through EXTI interrupt */
VECTAB_ENTRY(OTG_HS_IRQ), /* USB OTG HS global interrupt */
VECTAB_ENTRY(DCMI_IRQ), /* DCMI global interrupt */
VECTAB_ENTRY(CRYP_IRQ), /* CRYP crypto global interrupt */
VECTAB_ENTRY(HASH_RNG_IRQ), /* Hash and Rng global interrupt */
};