[dev][bus][pci] move the pci driver out of platform/pc into generic space
No functional change.
This commit is contained in:
Travis Geiselbrecht
@@ -1,164 +0,0 @@
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/*
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* Copyright (c) 2009 Corey Tabaka
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#pragma once
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#include <sys/types.h>
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#include <lk/compiler.h>
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/*
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* PCI access return codes
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*/
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#define _PCI_SUCCESSFUL 0x00
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#define _PCI_FUNC_NOT_SUPPORTED 0x81
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#define _PCI_BAD_VENDOR_ID 0x83
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#define _PCI_DEVICE_NOT_FOUND 0x86
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#define _PCI_BAD_REGISTER_NUMBER 0x87
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#define _PCI_SET_FAILED 0x88
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#define _PCI_BUFFER_TOO_SMALL 0x89
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/*
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* PCI configuration space offsets
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*/
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#define PCI_CONFIG_VENDOR_ID 0x00
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#define PCI_CONFIG_DEVICE_ID 0x02
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#define PCI_CONFIG_COMMAND 0x04
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#define PCI_CONFIG_STATUS 0x06
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#define PCI_CONFIG_REVISION_ID 0x08
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#define PCI_CONFIG_CLASS_CODE 0x09
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#define PCI_CONFIG_CLASS_CODE_INTR 0x09
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#define PCI_CONFIG_CLASS_CODE_SUB 0x0a
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#define PCI_CONFIG_CLASS_CODE_BASE 0x0b
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#define PCI_CONFIG_CACHE_LINE_SIZE 0x0c
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#define PCI_CONFIG_LATENCY_TIMER 0x0d
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#define PCI_CONFIG_HEADER_TYPE 0x0e
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#define PCI_CONFIG_BIST 0x0f
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#define PCI_CONFIG_BASE_ADDRESSES 0x10
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#define PCI_CONFIG_CARDBUS_CIS_PTR 0x28
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#define PCI_CONFIG_SUBSYS_VENDOR_ID 0x2c
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#define PCI_CONFIG_SUBSYS_ID 0x2e
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#define PCI_CONFIG_EXP_ROM_ADDRESS 0x30
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#define PCI_CONFIG_CAPABILITIES 0x34
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#define PCI_CONFIG_INTERRUPT_LINE 0x3c
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#define PCI_CONFIG_INTERRUPT_PIN 0x3d
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#define PCI_CONFIG_MIN_GRANT 0x3e
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#define PCI_CONFIG_MAX_LATENCY 0x3f
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/*
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* PCI header type register bits
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*/
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#define PCI_HEADER_TYPE_MASK 0x7f
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#define PCI_HEADER_TYPE_MULTI_FN 0x80
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/*
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* PCI header types
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*/
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#define PCI_HEADER_TYPE_STANDARD 0x00
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#define PCI_HEADER_TYPE_PCI_BRIDGE 0x01
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#define PCI_HEADER_TYPE_CARD_BUS 0x02
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/*
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* PCI command register bits
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*/
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#define PCI_COMMAND_IO_EN 0x0001
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#define PCI_COMMAND_MEM_EN 0x0002
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#define PCI_COMMAND_BUS_MASTER_EN 0x0004
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#define PCI_COMMAND_SPECIAL_EN 0x0008
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#define PCI_COMMAND_MEM_WR_INV_EN 0x0010
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#define PCI_COMMAND_PAL_SNOOP_EN 0x0020
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#define PCI_COMMAND_PERR_RESP_EN 0x0040
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#define PCI_COMMAND_AD_STEP_EN 0x0080
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#define PCI_COMMAND_SERR_EN 0x0100
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#define PCI_COMMAND_FAST_B2B_EN 0x0200
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/*
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* PCI status register bits
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*/
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#define PCI_STATUS_NEW_CAPS 0x0010
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#define PCI_STATUS_66_MHZ 0x0020
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#define PCI_STATUS_FAST_B2B 0x0080
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#define PCI_STATUS_MSTR_PERR 0x0100
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#define PCI_STATUS_DEVSEL_MASK 0x0600
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#define PCI_STATUS_TARG_ABORT_SIG 0x0800
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#define PCI_STATUS_TARG_ABORT_RCV 0x1000
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#define PCI_STATUS_MSTR_ABORT_RCV 0x2000
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#define PCI_STATUS_SERR_SIG 0x4000
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#define PCI_STATUS_PERR 0x8000
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typedef struct {
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uint16_t vendor_id;
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uint16_t device_id;
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uint16_t command;
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uint16_t status;
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uint8_t revision_id_0;
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uint8_t program_interface;
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uint8_t sub_class;
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uint8_t base_class;
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uint8_t cache_line_size;
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uint8_t latency_timer;
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uint8_t header_type;
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uint8_t bist;
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uint32_t base_addresses[6];
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uint32_t cardbus_cis_ptr;
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uint16_t subsystem_vendor_id;
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uint16_t subsystem_id;
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uint32_t expansion_rom_address;
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uint8_t capabilities_ptr;
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uint8_t reserved_0[3];
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uint32_t reserved_1;
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uint8_t interrupt_line;
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uint8_t interrupt_pin;
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uint8_t min_grant;
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uint8_t max_latency;
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} __PACKED pci_config_t;
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/*
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* PCI address structure
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*/
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typedef struct {
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uint8_t bus;
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uint8_t dev_fn;
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} pci_location_t;
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typedef struct {
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uint8_t id;
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uint8_t next;
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} __PACKED pci_capability_t;
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typedef struct {
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uint8_t bus;
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uint8_t device;
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uint8_t link_int_a;
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uint16_t irq_int_a;
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uint8_t link_int_b;
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uint16_t irq_int_b;
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uint8_t link_int_c;
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uint16_t irq_int_c;
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uint8_t link_int_d;
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uint16_t irq_int_d;
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uint8_t slot;
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uint8_t reserved;
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} __PACKED irq_routing_entry;
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void pci_init(void);
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int pci_get_last_bus(void);
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int pci_find_pci_device(pci_location_t *state, uint16_t device_id, uint16_t vendor_id, uint16_t index);
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int pci_find_pci_class_code(pci_location_t *state, uint32_t class_code, uint16_t index);
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int pci_read_config_byte(const pci_location_t *state, uint32_t reg, uint8_t *value);
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int pci_read_config_half(const pci_location_t *state, uint32_t reg, uint16_t *value);
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int pci_read_config_word(const pci_location_t *state, uint32_t reg, uint32_t *value);
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int pci_write_config_byte(const pci_location_t *state, uint32_t reg, uint8_t value);
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int pci_write_config_half(const pci_location_t *state, uint32_t reg, uint16_t value);
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int pci_write_config_word(const pci_location_t *state, uint32_t reg, uint32_t value);
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int pci_get_irq_routing_options(irq_routing_entry *entries, uint16_t *count, uint16_t *pci_irqs);
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int pci_set_irq_hw_int(const pci_location_t *state, uint8_t int_pin, uint8_t irq);
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