From a04776ba78be764a3a3203819047c69de57f32b5 Mon Sep 17 00:00:00 2001 From: Travis Geiselbrecht Date: Fri, 11 Apr 2025 01:20:14 -0700 Subject: [PATCH] [arch][x86] add a few more feature bits There's always more feature bits showing up on these things. Rename a few to match the intel manual closer. --- arch/x86/64/mmu.c | 2 +- arch/x86/include/arch/x86/feature.h | 21 +++++++++++++++------ 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/arch/x86/64/mmu.c b/arch/x86/64/mmu.c index 8f9dbca8..56926310 100644 --- a/arch/x86/64/mmu.c +++ b/arch/x86/64/mmu.c @@ -658,7 +658,7 @@ void x86_mmu_early_init(void) { vaddr_width = x86_get_vaddr_width(); /* check to see if we support huge (1GB) and invpcid instruction */ - supports_huge_pages = x86_feature_test(X86_FEATURE_HUGE_PAGE); + supports_huge_pages = x86_feature_test(X86_FEATURE_PG1G); supports_invpcid = x86_feature_test(X86_FEATURE_INVPCID); supports_pcid = x86_feature_test(X86_FEATURE_PCID); diff --git a/arch/x86/include/arch/x86/feature.h b/arch/x86/include/arch/x86/feature.h index a743a634..7d4864b5 100644 --- a/arch/x86/include/arch/x86/feature.h +++ b/arch/x86/include/arch/x86/feature.h @@ -209,6 +209,7 @@ static inline bool x86_feature_test(struct x86_cpuid_bit bit) { #define X86_FEATURE_XSAVE X86_CPUID_BIT(0x1, 2, 26) #define X86_FEATURE_OSXSAVE X86_CPUID_BIT(0x1, 2, 27) #define X86_FEATURE_AVX X86_CPUID_BIT(0x1, 2, 28) +#define X86_FEATURE_F16C X86_CPUID_BIT(0x1, 2, 29) #define X86_FEATURE_RDRAND X86_CPUID_BIT(0x1, 2, 30) #define X86_FEATURE_HYPERVISOR X86_CPUID_BIT(0x1, 2, 31) #define X86_FEATURE_FPU X86_CPUID_BIT(0x1, 3, 0) @@ -250,16 +251,17 @@ static inline bool x86_feature_test(struct x86_cpuid_bit bit) { #define X86_FEATURE_HWP X86_CPUID_BIT(0x6, 0, 7) #define X86_FEATURE_HWP_NOT X86_CPUID_BIT(0x6, 0, 8) #define X86_FEATURE_HWP_ACT X86_CPUID_BIT(0x6, 0, 9) -#define X86_FEATURE_HWP_PREF X86_CPUID_BIT(0x6, 0, 10) -#define X86_FEATURE_HWP_EPP X86_CPUID_BIT(0x6, 0, 11) -#define X86_FEATURE_HWP_PKG X86_CPUID_BIT(0x6, 0, 12) +#define X86_FEATURE_HWP_EPP X86_CPUID_BIT(0x6, 0, 10) +#define X86_FEATURE_HWP_PKG X86_CPUID_BIT(0x6, 0, 11) #define X86_FEATURE_HDC X86_CPUID_BIT(0x6, 0, 13) #define X86_FEATURE_TURBO_MAX X86_CPUID_BIT(0x6, 0, 14) #define X86_FEATURE_HWP_CAP X86_CPUID_BIT(0x6, 0, 15) #define X86_FEATURE_HWP_PECI X86_CPUID_BIT(0x6, 0, 16) #define X86_FEATURE_HWP_FLEX X86_CPUID_BIT(0x6, 0, 17) #define X86_FEATURE_HWP_FAST X86_CPUID_BIT(0x6, 0, 18) -#define X86_FEATURE_HW_FEEDBACK X86_CPUID_BIT(0x6, 2, 0) +#define X86_FEATURE_HW_FEEDBACK X86_CPUID_BIT(0x6, 0, 19) +#define X86_FEATURE_THREAD_DIR X86_CPUID_BIT(0x6, 0, 23) +#define X86_FEATURE_MPERF X86_CPUID_BIT(0x6, 2, 0) #define X86_FEATURE_PERF_BIAS X86_CPUID_BIT(0x6, 2, 3) #define X86_FEATURE_FSGSBASE X86_CPUID_BIT(0x7, 1, 0) @@ -268,12 +270,16 @@ static inline bool x86_feature_test(struct x86_cpuid_bit bit) { #define X86_FEATURE_BMI1 X86_CPUID_BIT(0x7, 1, 3) #define X86_FEATURE_HLE X86_CPUID_BIT(0x7, 1, 4) #define X86_FEATURE_AVX2 X86_CPUID_BIT(0x7, 1, 5) +#define X86_FEATURE_FPDP X86_CPUID_BIT(0x7, 1, 6) #define X86_FEATURE_SMEP X86_CPUID_BIT(0x7, 1, 7) #define X86_FEATURE_BMI2 X86_CPUID_BIT(0x7, 1, 8) #define X86_FEATURE_ERMS X86_CPUID_BIT(0x7, 1, 9) #define X86_FEATURE_INVPCID X86_CPUID_BIT(0x7, 1, 10) #define X86_FEATURE_RTM X86_CPUID_BIT(0x7, 1, 11) +#define X86_FEATURE_PQM X86_CPUID_BIT(0x7, 1, 12) +#define X86_FEATURE_FPCSDS X86_CPUID_BIT(0x7, 1, 13) #define X86_FEATURE_MPX X86_CPUID_BIT(0x7, 1, 14) +#define X86_FEATURE_PQE X86_CPUID_BIT(0x7, 1, 15) #define X86_FEATURE_AVX512F X86_CPUID_BIT(0x7, 1, 16) #define X86_FEATURE_AVX512DQ X86_CPUID_BIT(0x7, 1, 17) #define X86_FEATURE_RDSEED X86_CPUID_BIT(0x7, 1, 18) @@ -348,14 +354,17 @@ static inline bool x86_feature_test(struct x86_cpuid_bit bit) { #define X86_FEATURE_KVM_CLOCKSOURCE_STABLE X86_CPUID_BIT(0x40000001, 0, 24) +#define X86_FEATURE_AHF64 X86_CPUID_BIT(0x80000001, 2, 0) +#define X86_FEATURE_LZCNT X86_CPUID_BIT(0x80000001, 2, 5) +#define X86_FEATURE_PREFETCHW X86_CPUID_BIT(0x80000001, 2, 8) #define X86_FEATURE_AMD_TOPO X86_CPUID_BIT(0x80000001, 2, 22) #define X86_FEATURE_SSE4A X86_CPUID_BIT(0x80000001, 3, 6) #define X86_FEATURE_SYSCALL X86_CPUID_BIT(0x80000001, 3, 11) #define X86_FEATURE_NX X86_CPUID_BIT(0x80000001, 3, 20) -#define X86_FEATURE_HUGE_PAGE X86_CPUID_BIT(0x80000001, 3, 26) +#define X86_FEATURE_PG1G X86_CPUID_BIT(0x80000001, 3, 26) #define X86_FEATURE_RDTSCP X86_CPUID_BIT(0x80000001, 3, 27) +#define X86_FEATURE_LM X86_CPUID_BIT(0x80000001, 3, 29) #define X86_FEATURE_INVAR_TSC X86_CPUID_BIT(0x80000007, 3, 8) -#define X86_FEATURE_CONSTANT_TSC X86_CPUID_BIT(0x80000007, 3, 8) // accessor to read some fields out of a register static inline uint32_t x86_get_vaddr_width(void) {