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[zynq] Convert clk/mio jam table to readable code

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Also re-added the generated pll table for documentation purposes
This commit is contained in:
Chris Anderson
2014-08-01 15:36:16 -07:00
parent e846e9e32e
commit 98a09511e9
3 changed files with 203 additions and 12 deletions
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65
platform/zynq/include/platform/zynq.h
View File

@@ -344,19 +344,68 @@ STATIC_ASSERT(offsetof(struct slcr_regs, DDRIOB_DCI_STATUS) == 0xb74);
#define PLL_STATUS_DDR_PLL_STABLE (1 << 4)
#define PLL_STATUS_IO_PLL_STABLE (1 << 5)
/* Generic clock control */
#define CLK_CTRL_CLKACT1 (1)
#define CLK_CTRL_CLKACT2 (1 << 1)
#define CLK_CTRL_SRCSEL(x) ((x & BIT_MASK(2)) << 4)
#define CLK_CTRL_DIVISOR1(x) ((x & BIT_MASK(6)) << 8)
#define CLK_CTRL_DIVISOR2(x) ((x & BIT_MASK(6)) << 20)
/* GEM clock control */
#define GEM_CLK_CTRL_SRCSEL(x) ((x & BIT_MASK(3)) << 4)
/* CLK 621 just has a single enable bit */
#define CLK_621_ENABLE (1)
/* AMBA Peripheral Clock Control */
#define SMC_CPU_CLK_EN (1 << 24)
#define LQSPI_CPU_CLK_EN (1 << 23)
#define GPIO_CPU_CLK_EN (1 << 22)
#define UART1_CPU_CLK_EN (1 << 21)
#define UART0_CPU_CLK_EN (1 << 20)
#define I2C1_CPU_CLK_EN (1 << 19)
#define I2C0_CPU_CLK_EN (1 << 18)
#define CAN1_CPU_CLK_EN (1 << 17)
#define CAN0_CPU_CLK_EN (1 << 16)
#define SPI1_CPU_CLK_EN (1 << 15)
#define SPI0_CPU_CLK_EN (1 << 14)
#define SDI1_CPU_CLK_EN (1 << 11)
#define SDI0_CPU_CLK_EN (1 << 10)
#define GEM1_CPU_CLK_EN (1 << 7)
#define GEM0_CPU_CLK_EN (1 << 6)
#define USB1_CPU_CLK_EN (1 << 3)
#define USB0_CPU_CLK_EN (1 << 2)
#define DMA_CPU_CLK_EN (1 << 0)
/* GPIOB_CTRL */
#define GPIOB_CTRL_VREF_09_EN (1 << 4)
#define GPIOB_CTRL_VREF_EN (1)
/* DDRIOB_ADDR */
#define DDRIOB_PULLUP_EN (1 << 11)
#define DDRIOB_OUTPUT_EN(x) ((x & BIT_MASK(2)) << 9)
#define DDRIOB_TERM_DISABLE_MODE (1 << 8)
#define DDRIOB_IBUF_DISABLE_MODE (1 << 7)
#define DDRIOB_DCI_TYPE(x) ((x & BIT_MASK(2)) << 5)
#define DDRIOB_TERM_EN (1 << 4)
#define DDRIOB_DCI_UPDATE_B (1 << 3)
#define DDRIOB_INP_TYPE(x) ((x & BIT_MASK(2)) << 1)
/* SD1_WP_CD_SEL */
#define SDIO0_WP_SEL(x) (x & BIT_MASK(6))
#define SDIO0_CD_SEL(x) ((x & BIT_MASK(6)) << 16)
/* MIO pin configuration */
#define MIO_TRI_ENABLE (1)
#define MIO_L0_SEL (1 << 1)
#define MIO_L1_SEL (1 << 2)
#define MIO_L2_SEL(x) (x << 3)
#define MIO_L3_SEL(x) (x << 5)
#define MIO_IO_TYPE_HSTL MIO_IO_TYPE(0x4)
#define MIO_L2_SEL(x) ((x & BIT_MASK(2)) << 3)
#define MIO_L3_SEL(x) ((x & BIT_MASK(3)) << 5)
#define MIO_SPEED_FAST (1 << 8)
#define MIO_IO_TYPE(x) (x << 9)
#define MIO_IO_TYPE_LVCMOS18 MIO_IO_TYPE(0x1)
#define MIO_IO_TYPE_LVCMOS25 MIO_IO_TYPE(0x2)
#define MIO_IO_TYPE_LVCMOS33 MIO_IO_TYPE(0x3)
#define MIO_IO_TYPE_HSTL MIO_IO_TYPE(0x4)
#define MIO_IO_TYPE_LVCMOS18 (0x1 << 9)
#define MIO_IO_TYPE_LVCMOS25 (0x2 << 9)
#define MIO_IO_TYPE_LVCMOS33 (0x3 << 9)
#define MIO_IO_TYPE_HSTL (0x4 << 9)
#define MIO_PULLUP (1 << 12)
#define MIO_DISABLE_RCVR (1 << 13)

9
platform/zynq/platform.c
View File

@@ -61,7 +61,6 @@ struct mmu_initial_mapping mmu_initial_mappings[] = {
.size = (16*1024*1024),
.flags = MMU_INITIAL_MAPPING_FLAG_UNCACHED,
.name = "axi1" },
/* 0xe0000000 hardware devices */
{ .phys = 0xe0000000,
.virt = 0xe0000000,
@@ -164,5 +163,13 @@ void platform_init(void)
printf("\tBOOT_MODE 0x%x\n", SLCR_REG(BOOT_MODE));
zynq_dump_clocks();
printf("zynq mio:\n");
for (size_t i = 0; i < 54; i++) {
printf("\t%02u: 0x%08x", i, *REG32((uintptr_t)&SLCR->MIO_PIN_00 + (i * 4)));
if (i % 4 == 3 || i == 53) {
putchar('\n');
}
}
}

141
target/zybo/init.c
View File

@@ -111,7 +111,8 @@ int zynq_pll_init(void) {
}
SLCR_REG(DDR_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
SLCR_REG(DDR_CLK_CTRL) = DDR_CLK_CTRL_DDR_3XCLKACT | DDR_CLK_CTRL_DDR_2XCLKACT | DDR_CLK_CTRL_DDR_3XCLK_DIV(3) | DDR_CLK_CTRL_DDR_2XCLK_DIV(2);
SLCR_REG(DDR_CLK_CTRL) = DDR_CLK_CTRL_DDR_3XCLKACT | DDR_CLK_CTRL_DDR_2XCLKACT |
DDR_CLK_CTRL_DDR_3XCLK_DIV(2) | DDR_CLK_CTRL_DDR_2XCLK_DIV(3);
/* IO PLL config
* 500 cycles needed for pll
@@ -131,6 +132,140 @@ int zynq_pll_init(void) {
return 0;
}
int zynq_clk_init(void)
{
zynq_slcr_unlock();
SLCR_REG(DCI_CLK_CTRL) = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR1(52) | CLK_CTRL_DIVISOR2(2);
SLCR_REG(GEM0_RCLK_CTRL) = CLK_CTRL_CLKACT1;
SLCR_REG(GEM0_CLK_CTRL) = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR1(8) | CLK_CTRL_DIVISOR2(1);
SLCR_REG(LQSPI_CLK_CTRL) = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR1(5);
SLCR_REG(SDIO_CLK_CTRL) = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR1(20);
SLCR_REG(UART_CLK_CTRL) = CLK_CTRL_CLKACT2 | CLK_CTRL_DIVISOR1(20);
SLCR_REG(PCAP_CLK_CTRL) = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR1(5);
SLCR_REG(FPGA0_CLK_CTRL) = CLK_CTRL_DIVISOR1(10) | CLK_CTRL_DIVISOR2(1);
SLCR_REG(FPGA1_CLK_CTRL) = CLK_CTRL_SRCSEL(3) | CLK_CTRL_DIVISOR1(6) | CLK_CTRL_DIVISOR2(1);
SLCR_REG(FPGA2_CLK_CTRL) = CLK_CTRL_SRCSEL(2) | CLK_CTRL_DIVISOR1(53) | CLK_CTRL_DIVISOR2(2);
SLCR_REG(FPGA3_CLK_CTRL) = CLK_CTRL_DIVISOR2(1);
SLCR_REG(CLK_621_TRUE) = CLK_621_ENABLE;
SLCR_REG(APER_CLK_CTRL) = DMA_CPU_CLK_EN | USB0_CPU_CLK_EN | USB1_CPU_CLK_EN |
GEM0_CPU_CLK_EN | SDI0_CPU_CLK_EN | I2C0_CPU_CLK_EN |
I2C1_CPU_CLK_EN | UART1_CPU_CLK_EN | GPIO_CPU_CLK_EN |
LQSPI_CPU_CLK_EN | SMC_CPU_CLK_EN;
zynq_slcr_lock();
return 0;
}
int zynq_mio_init(void)
{
zynq_slcr_unlock();
SLCR_REG(GPIOB_CTRL) = GPIOB_CTRL_VREF_EN;
SLCR_REG(DDRIOB_ADDR0) = DDRIOB_OUTPUT_EN(0x3);
SLCR_REG(DDRIOB_ADDR1) = DDRIOB_OUTPUT_EN(0x3);
SLCR_REG(DDRIOB_DATA0) = DDRIOB_INP_TYPE(1) | DDRIOB_TERM_EN |
DDRIOB_DCI_TYPE(0x3) | DDRIOB_OUTPUT_EN(0x3);
SLCR_REG(DDRIOB_DATA1) = DDRIOB_INP_TYPE(1) | DDRIOB_TERM_EN |
DDRIOB_DCI_TYPE(0x3) | DDRIOB_OUTPUT_EN(0x3);
SLCR_REG(DDRIOB_DIFF0) = DDRIOB_INP_TYPE(2) | DDRIOB_TERM_EN |
DDRIOB_DCI_TYPE(0x3) | DDRIOB_OUTPUT_EN(0x3);
SLCR_REG(DDRIOB_DIFF1) = DDRIOB_INP_TYPE(2) | DDRIOB_TERM_EN |
DDRIOB_DCI_TYPE(0x3) | DDRIOB_OUTPUT_EN(0x3);
SLCR_REG(DDRIOB_CLOCK) = DDRIOB_OUTPUT_EN(0x3);
/* These register fields are not documented in the TRM. These
* values represent the defaults generated via the Zynq tools
*/
SLCR_REG(DDRIOB_DRIVE_SLEW_ADDR) = 0x0018C61CU;
SLCR_REG(DDRIOB_DRIVE_SLEW_DATA) = 0x00F9861CU;
SLCR_REG(DDRIOB_DRIVE_SLEW_DIFF) = 0x00F9861CU;
SLCR_REG(DDRIOB_DRIVE_SLEW_CLOCK) = 0x00F9861CU;
SLCR_REG(DDRIOB_DDR_CTRL) = 0x00000E60U;
SLCR_REG(DDRIOB_DCI_CTRL) = 0x00000001U;
SLCR_REG(DDRIOB_DCI_CTRL) |= 0x00000020U;
SLCR_REG(DDRIOB_DCI_CTRL) |= 0x00000823U;
/* mio pin config */
SLCR_REG(MIO_PIN_01) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33;
SLCR_REG(MIO_PIN_02) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33;
SLCR_REG(MIO_PIN_03) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33;
SLCR_REG(MIO_PIN_04) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33;
SLCR_REG(MIO_PIN_05) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33;
SLCR_REG(MIO_PIN_06) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33;
SLCR_REG(MIO_PIN_08) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33;
SLCR_REG(MIO_PIN_16) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_DISABLE_RCVR;
SLCR_REG(MIO_PIN_17) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_DISABLE_RCVR;
SLCR_REG(MIO_PIN_18) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_DISABLE_RCVR;
SLCR_REG(MIO_PIN_19) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_DISABLE_RCVR;
SLCR_REG(MIO_PIN_20) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_DISABLE_RCVR;
SLCR_REG(MIO_PIN_21) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_DISABLE_RCVR;
SLCR_REG(MIO_PIN_22) = MIO_TRI_ENABLE | MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL;
SLCR_REG(MIO_PIN_23) = MIO_TRI_ENABLE | MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL;
SLCR_REG(MIO_PIN_24) = MIO_TRI_ENABLE | MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL;
SLCR_REG(MIO_PIN_25) = MIO_TRI_ENABLE | MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL;
SLCR_REG(MIO_PIN_26) = MIO_TRI_ENABLE | MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL;
SLCR_REG(MIO_PIN_27) = MIO_TRI_ENABLE | MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL;
SLCR_REG(MIO_PIN_28) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_29) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18 | MIO_TRI_ENABLE;
SLCR_REG(MIO_PIN_30) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_31) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18 | MIO_TRI_ENABLE;
SLCR_REG(MIO_PIN_32) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_33) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_34) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_35) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_36) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18 | MIO_TRI_ENABLE;
SLCR_REG(MIO_PIN_37) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_38) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_39) = MIO_L1_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_40) = MIO_L3_SEL(0x4) | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_41) = MIO_L3_SEL(0x4) | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_42) = MIO_L3_SEL(0x4) | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_43) = MIO_L3_SEL(0x4) | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_44) = MIO_L3_SEL(0x4) | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_45) = MIO_L3_SEL(0x4) | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_47) = MIO_TRI_ENABLE | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_48) = MIO_L3_SEL(0x7) | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_49) = MIO_TRI_ENABLE | MIO_L3_SEL(0x7) | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_52) = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(MIO_PIN_53) = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18;
SLCR_REG(SD0_WP_CD_SEL) = SDIO0_WP_SEL(0x37) | SDIO0_CD_SEL(0x2F);
zynq_slcr_lock();
return 0;
}
static const unsigned long ps7_pll_init_data_3_0[] = {
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001772C0U),
EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001A000U),
EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
EMIT_MASKPOLL(0XF800010C, 0x00000001U),
EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001DB2C0U),
EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00015000U),
EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
EMIT_MASKPOLL(0XF800010C, 0x00000002U),
EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001F42C0U),
EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00014000U),
EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
EMIT_MASKPOLL(0XF800010C, 0x00000004U),
EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
EMIT_EXIT(),
};
static const unsigned long ps7_clock_init_data_3_0[] = {
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203401U),
@@ -430,7 +565,7 @@ int ps7_init(void)
int ret;
// MIO init
ret = ps7_config (ps7_mio_init_data_3_0);
ret = zynq_mio_init();
if (ret != PS7_INIT_SUCCESS) return ret;
// PLL init
@@ -438,7 +573,7 @@ int ps7_init(void)
if (ret != PS7_INIT_SUCCESS) return ret;
// Clock init
ret = ps7_config (ps7_clock_init_data_3_0);
ret = zynq_clk_init();
if (ret != PS7_INIT_SUCCESS) return ret;
// DDR init