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[dev][cache][pl310] add routine to pin cache lines in the L2

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NOTE: assumes the LOCK_LINE_EN feature is present.
This commit is contained in:
Travis Geiselbrecht
2015-04-03 21:15:19 -07:00
parent bab2e8ccf5
commit 94cf843de1
2 changed files with 26 additions and 0 deletions
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2
dev/cache/pl310/include/dev/cache/pl310.h vendored
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@@ -34,3 +34,5 @@ void pl310_sync_range(void);
void pl310_clean_range(addr_t start, size_t len);
void pl310_clean_invalidate_range(addr_t start, size_t len);
void pl310_invalidate_range(addr_t start, size_t len);
void pl310_pin_cache_range(addr_t start, size_t len);

24
dev/cache/pl310/pl310.c vendored
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@@ -26,6 +26,7 @@
#include <trace.h>
#include <err.h>
#include <reg.h>
#include <stdlib.h>
#include <arch.h>
#include <arch/arm/mmu.h>
#include <dev/cache/pl310_config.h>
@@ -203,3 +204,26 @@ void pl310_invalidate_range(addr_t start, size_t len)
PL310_LOOP_BODY(REG7_INV_PA);
}
void pl310_pin_cache_range(addr_t start, size_t len)
{
len = ROUNDUP(len, CACHE_LINE);
arch_disable_ints();
arch_clean_invalidate_cache_range(start, len);
PL310_REG(REG9_LOCK_LINE_EN) = 1;
DSB;
while (len > 0) {
asm volatile("pld [%0]" :: "r"(start) : "memory");
start += CACHE_LINE;
len -= CACHE_LINE;
}
DSB;
PL310_REG(REG9_LOCK_LINE_EN) = 0;
arch_enable_ints();
}