[bus][pci] Clarify device::assign_resource
The previous XXX comments were unnecessary as the spec defines the bottom 3 bits as being hardwired and read-only.
This commit is contained in:
committed by
Travis Geiselbrecht
parent
3b4dade91f
commit
93a8b45ada
@@ -550,18 +550,21 @@ status_t device::assign_resource(bar_alloc_request *request, uint64_t address) {
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DEBUG_ASSERT(IS_ALIGNED(address, (1UL << request->align)));
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DEBUG_ASSERT(IS_ALIGNED(address, (1UL << request->align)));
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// Note: When assigning the resource, we don't bother setting the bottom bits
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// as those are hardwired per the spec.
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uint32_t temp;
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uint32_t temp;
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switch (request->type) {
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switch (request->type) {
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case PCI_RESOURCE_IO_RANGE:
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case PCI_RESOURCE_IO_RANGE:
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temp = (address & 0xfffc); // XXX do we need to write the bottom bits?
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temp = (address & 0xfffc);
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pci_write_config_word(loc(), PCI_CONFIG_BASE_ADDRESSES + request->bar_num * 4, temp);
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pci_write_config_word(loc(), PCI_CONFIG_BASE_ADDRESSES + request->bar_num * 4, temp);
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break;
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break;
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case PCI_RESOURCE_MMIO_RANGE:
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case PCI_RESOURCE_MMIO_RANGE:
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temp = (address & 0xfffffff0); // XXX do we need to write the bottom bits?
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temp = (address & 0xfffffff0);
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pci_write_config_word(loc(), PCI_CONFIG_BASE_ADDRESSES + request->bar_num * 4, temp);
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pci_write_config_word(loc(), PCI_CONFIG_BASE_ADDRESSES + request->bar_num * 4, temp);
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break;
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break;
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case PCI_RESOURCE_MMIO64_RANGE:
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case PCI_RESOURCE_MMIO64_RANGE:
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temp = (address & 0xfffffff0); // XXX do we need to write the bottom bits?
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temp = (address & 0xfffffff0);
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pci_write_config_word(loc(), PCI_CONFIG_BASE_ADDRESSES + request->bar_num * 4, temp);
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pci_write_config_word(loc(), PCI_CONFIG_BASE_ADDRESSES + request->bar_num * 4, temp);
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temp = address >> 32;
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temp = address >> 32;
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pci_write_config_word(loc(), PCI_CONFIG_BASE_ADDRESSES + request->bar_num * 4 + 4, temp);
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pci_write_config_word(loc(), PCI_CONFIG_BASE_ADDRESSES + request->bar_num * 4 + 4, temp);
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