lby/lk
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

[bus][pci] Clarify device::assign_resource

Browse Source 
The previous XXX comments were unnecessary as the spec defines the
bottom 3 bits as being hardwired and read-only.
This commit is contained in:
Pedro Falcato
2022-12-31 03:14:45 +00:00
committed by Travis Geiselbrecht
parent 3b4dade91f
commit 93a8b45ada
1 changed files with 6 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
dev/bus/pci/bus_mgr/device.cpp
View File

@@ -550,18 +550,21 @@ status_t device::assign_resource(bar_alloc_request *request, uint64_t address) {
DEBUG_ASSERT(IS_ALIGNED(address, (1UL << request->align)));
// Note: When assigning the resource, we don't bother setting the bottom bits
// as those are hardwired per the spec.
uint32_t temp;
switch (request->type) {
case PCI_RESOURCE_IO_RANGE:
temp = (address & 0xfffc); // XXX do we need to write the bottom bits?
temp = (address & 0xfffc);
pci_write_config_word(loc(), PCI_CONFIG_BASE_ADDRESSES + request->bar_num * 4, temp);
break;
case PCI_RESOURCE_MMIO_RANGE:
temp = (address & 0xfffffff0); // XXX do we need to write the bottom bits?
temp = (address & 0xfffffff0);
pci_write_config_word(loc(), PCI_CONFIG_BASE_ADDRESSES + request->bar_num * 4, temp);
break;
case PCI_RESOURCE_MMIO64_RANGE:
temp = (address & 0xfffffff0); // XXX do we need to write the bottom bits?
temp = (address & 0xfffffff0);
pci_write_config_word(loc(), PCI_CONFIG_BASE_ADDRESSES + request->bar_num * 4, temp);
temp = address >> 32;
pci_write_config_word(loc(), PCI_CONFIG_BASE_ADDRESSES + request->bar_num * 4 + 4, temp);