From 93a8b45adad260715d924da2afa4f56dae5e0518 Mon Sep 17 00:00:00 2001 From: Pedro Falcato Date: Sat, 31 Dec 2022 03:14:45 +0000 Subject: [PATCH] [bus][pci] Clarify device::assign_resource The previous XXX comments were unnecessary as the spec defines the bottom 3 bits as being hardwired and read-only. --- dev/bus/pci/bus_mgr/device.cpp | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/dev/bus/pci/bus_mgr/device.cpp b/dev/bus/pci/bus_mgr/device.cpp index c2903ca4..ac071d63 100644 --- a/dev/bus/pci/bus_mgr/device.cpp +++ b/dev/bus/pci/bus_mgr/device.cpp @@ -550,18 +550,21 @@ status_t device::assign_resource(bar_alloc_request *request, uint64_t address) { DEBUG_ASSERT(IS_ALIGNED(address, (1UL << request->align))); + // Note: When assigning the resource, we don't bother setting the bottom bits + // as those are hardwired per the spec. + uint32_t temp; switch (request->type) { case PCI_RESOURCE_IO_RANGE: - temp = (address & 0xfffc); // XXX do we need to write the bottom bits? + temp = (address & 0xfffc); pci_write_config_word(loc(), PCI_CONFIG_BASE_ADDRESSES + request->bar_num * 4, temp); break; case PCI_RESOURCE_MMIO_RANGE: - temp = (address & 0xfffffff0); // XXX do we need to write the bottom bits? + temp = (address & 0xfffffff0); pci_write_config_word(loc(), PCI_CONFIG_BASE_ADDRESSES + request->bar_num * 4, temp); break; case PCI_RESOURCE_MMIO64_RANGE: - temp = (address & 0xfffffff0); // XXX do we need to write the bottom bits? + temp = (address & 0xfffffff0); pci_write_config_word(loc(), PCI_CONFIG_BASE_ADDRESSES + request->bar_num * 4, temp); temp = address >> 32; pci_write_config_word(loc(), PCI_CONFIG_BASE_ADDRESSES + request->bar_num * 4 + 4, temp);